User Adoption of OVM Featured; Views on UVM Discussed
The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set. U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens.
Registration for the event is open and is fee-free. U2U … Read More
Mentor Blogs
Posts tagged with 'VIP'
The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs.
Accellera’s Verification IP (VIP) Technical … Read More
UVM, Universal Verification Methodology, Milaero, Design Automation, Open Verification Methodology, OVM, TSC, Accellera, IC, Mentor, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP
DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys
The full statement can be read at EDA Cafe, click here.
The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More
Download OVM Configuration and Virtual Interface Extensions from OVMWorld.org
Creating configurable testbench elements is critical for reuse. If you write some OVM code in one particular testbench and never intend to use it in any other testbench, then there is no need to make it configurable. As soon as you wish to take code and turn it into reusable IP which can be used in a variety of applications, … Read More
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