Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been … Read More
Mentor Blogs
Posts tagged with 'VMM'
Historical Perspective
In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and … Read More
DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys
The full statement can be read at EDA Cafe, click here.
The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More
3 – 2 – 1 – DOWNLOAD!
As I mentioned in a previous blog, the Accellera OVM/VMM Interoperability kit code that is a companion to the Verification Intellectual Property Recommended Practices (1MB PDF) was nearing readiness. As of today, it is now ready for download and use. With qualification tests run on verification platforms from the Big-3 EDA companies, no objection was voiced at a recent Accellera … Read More
Users Can Start Migration to OVM Today
Accellera’s Verification Intellectual Property (VIP) Technical Committee (TC) co-chair issued a public status report that highlights the group’s progress on its first phase of work, the OVM/VMM Interoperability Guide and companion software interoperability kit, and its second phase of work, a common base class library (CBCL) with OVM as its basis.
As the market … Read More
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VHDL-AMS Stress Modeling - Part 2
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U.S. DOT launches large V2V and V2I test
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Did you know this?
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Instant Replay for Debugging SoC Level Simulations
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ARM Development Conference
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