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Posts tagged with 'Yield'

14 Jan, 2014

Shelly Stalnaker Do you have a product that has been manufactured for quite some time at a high volume? If so, maybe it makes financial sense to chase down that last 1% of yield loss. In Geir Eide’s article on EDN.com, he explains how diagnosis-driven yield analysis (DDYA) can help you quickly and efficiently identify the root cause of yield loss, and separate design-based from process-based yield loss. Still … Read More

yield loss, Yield, diagnosis-drive yield analysis, Foundry, DDYA, root cause analysis, root cause deconvolution, layout-aware can diagnosis, RCD

6 Feb, 2013

Bernard Sutton Should we focus more on measuring the results, or the process that get us there? This is the constant balancing act that we all address. I personally prefer to work on the processes that ensure high quality. But without some measures on quality, how do we know these are working? Until someone invents a foolproof process, I would guess we still have to do both. We can, however, take steps to remove errors … Read More

lean manufacturing, FMEA, Manufacturing costs, zero defects, Yield, corrective action, PCBA, Quality, Defect opportunities, Route cause, CAPA, Manufacturing execution system, Manufacturing System Solution, Defects

5 Oct, 2012

Bernard Sutton I still get surprised, and occasionally disappointed, when I talk to production folk about quality. I still hear comments like, “our quality team deal with that”. or “we should talk to our Quality manager”. when what we are really talking about is making products error free. I guess we don’t help ourselves by using terms like ‘right first time’ & ’zero … Read More

PCBA, Quality, corrective action, Defect opportunities, CAPA, Route cause, Manufacturing execution system, Yield, Defects, zero defects, lean manufacturing

19 Jul, 2012

Bernard Sutton Did any one spot the misspelling of ‘Quality’ in the header of my last blog? I wish I could say it was a deliberate error to entice comments from my quality conscious readers. But sadly it was just an defect. One letter missing from around a thousand. Making my defect per million opportunity rate 1,000 DPMO. Believe me it would be much higher if it were not for spell checker. Back to the … Read More

Manufacturing execution system, lean manufacturing, Manufacturing System Solution, corrective action, Yield, Defect opportunities, CAPA, iNEMI, IPC, PCBA, Defects, Quality, dpmo

19 Jun, 2012

Bernard Sutton Test is not ‘Quality’: Firstly I should declare an interest; I am a test guy. I like the technical challenge of solving difficult test problems. And have been lucky to have worked on some interesting test challenges. But I still get surprised when I hear comments like “we have an extensive test process to ensure product Quality”. My surprise comes from my view, that whilst an … Read More

PCBA, corrective action, Crosby, Yield, zero defects, CAPA, Philip Crosby, Manufacturing execution system, Quality, Manufacturing System Solution, Route cause, lean manufacturing, test engineer, Manufacturing costs

20 Nov, 2009
IC Design

IBM Addresses Leakage

Posted by David Abercrombie

David Abercrombie

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield

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Physical Verification, Yield, DRC, Leakage, IC Design, Design Quality, IC Verification, Design for Manufacturing

20 Aug, 2009

David Abercrombie I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More

Reliability, IC Verification, Yield, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking

6 Aug, 2009
IC Design

David's DAC09 - Lunch & Learn

Posted by David Abercrombie

David Abercrombie My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP. It started … Read More

Design Quality, Design for Manufacturing, IP, Physical Verification, Yield

31 Jul, 2009
IC Design

David's DAC09 - Another Special Guest

Posted by David Abercrombie

David Abercrombie Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More

Reliability, IC Verification, Yield, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules

28 Jul, 2009
IC Design

David's DAC09 - Off to a great start!

Posted by David Abercrombie

David Abercrombie Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More

IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking

19 Jun, 2009

David Abercrombie One of the fundamental questions everyone asks about DFM is “why should I do it?” On the one hand this always strikes me as a funny question. I always look at DFM in the same way I think of automobile safety. Statistically, most people never get in a serious accident. So why would you spend so much money on airbags, antilock brakes, better seat belts, side door reinforcements, traction control, etc. … Read More

Yield, Design Quality, Design for Manufacturing, IC Verification, Reliability, Physical Verification, IC Design

5 Jun, 2009
IC Design

DFM for Non-PhDs

Posted by David Abercrombie

David Abercrombie

I got a kick out of Rohan’s comment on my previous blog (How do you define DFM?).  It is too easy to assume that anyone knows what you are talking about when you say DFM.  Just because everyone has been talking about it doesn’t mean any of them know what they are talking about. You could probably infer from my approach to the previous blog that my background is primarily on the manufacturing side.

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IC Design, Yield, IC Verification, Design Quality, Reliability, Design for Manufacturing

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