China Training Courses
Electrical & Wire Harness Design
FPGA
- ADiT for Fast-SPICE Simulation
- Artist Link
- Board Station RE
- C++ for Hardware Design
- CES for Board Station Flow
- CES for Expedition PCB
- Design Architect
- Design Architect/Library Management System
- DxDesigner for Expedition PCB Flow
- Eldo Simulation
- Expedition PCB Flow: Automation and Scripting
- HDL Designer Series
- HDL Designer Series Live Online
- I/O Designer
- ModelSim Advanced Topics
- ModelSim HDL Simulation
- Questa ADMS for A/MS Design Verification
- Questa Clock Domain Crossing Verification
- Questa Essentials
- Questa Formal Verification
- ReqTracer for FPGA/ASIC Design Assurance
- SystemVerilog for Verification
- VHDL Introduction
- VHDL-AMS (3 Day)
Functional Verification
- ADiT for Fast-SPICE Simulation
- Artist Link
- C++ for Hardware Design
- Certe OVM Testbench
- Eldo Simulation
- HDL Designer Series
- ModelSim Advanced Topics
- ModelSim HDL Simulation
- OVM to UVM Transition
- PSL: Assertion Based Verification with Questa
- Questa ADMS for A/MS Design Verification
- Questa Clock Domain Crossing Verification
- Questa Essentials
- Questa Formal Verification
- SystemVerilog for Verification
- SystemVerilog Open Verification Methodology
- SystemVerilog Universal Verification Methodology
- SystemVerilog Universal Verification Methodology Advanced
- Tessent Scan and ATPG
- Verilog Fundamentals for SystemVerilog
- Verilog Introduction
- VHDL Advanced
- VHDL Introduction
- VHDL-AMS (3 Day)
IC Design
- ADiT for Fast-SPICE Simulation
- Artist Link
- Calibre Advanced Topics: Mastering Calibre eqDRC
- Calibre Advanced Topics: nmLVS Debug Case Studies
- Calibre Advanced Topics: Writing PERC Rules
- Calibre DRC Optimization
- Calibre Fundamentals: DESIGNrev
- Calibre Fundamentals: Performing DRC/LVS
- Calibre Fundamentals: Working with PERC
- Calibre Fundamentals: Working with PERC Live Online
- Calibre Fundamentals: Writing DRC/LVS Rules
- Calibre RET
- Calibre TVF
- Calibre xRC Parasitic Extraction
- Eldo Basic Simulation
- Eldo Simulation
- HyperLynx Analog
- IC Design Flow With ICstudio
- PSL: Assertion Based Verification with Questa
- Questa ADMS for A/MS Design Verification
- VHDL-AMS (3 Day)
- VHDL-AMS (5 Day)
Intellectual Property
Mechanical Analysis
PCB Design Software & Tools
- Board Station Comprehensive
- Board Station RE
- Board Station XE
- CES for Board Station Flow
- CES for Board Station XE Flow
- CES for Expedition PCB
- Design Architect
- Design Architect/Library Management System
- Design Capture for Expedition PCB Layout
- DxDesigner for Expedition PCB Flow
- DxDesigner for PADS Flow
- Expedition PCB Advanced
- Expedition PCB Flow: Automation and Scripting
- Expedition PCB Introduction
- HyperLynx Advanced High-Speed PCB Analysis
- HyperLynx Analog
- HyperLynx Power Integrity Analysis
- HyperLynx Signal Integrity Analysis
- I/O Designer
- Library Manager for Design Capture to Expedition PCB
- Library Manager for DxDesigner to Expedition PCB Flow
- RF Design in DxD/Expedition
- vSure Introduction