Design-for-Test: Memory BIST
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Duration: 1 Day
Pricing: 1800 CNY
Course Part Number: 201975
Course Overview
The MBIST course is designed to drive the development of your skills and knowledge in the field of testing memories through the use of built-in-self-test concepts in a design flow utilizing Mentor Graphics MBISTArchitect tool. This course will teach you how to use MBISTArchitect software to create and incorporate built-in-self-test logic into your design for testing single or multiple memories (RAMs and ROMs), integrating generated BIST Hardware to SoC design, perform pattern translation, generate top level patterns, integration of BIST with JTAG controller.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with Mentor Graphics MBISTArchitect tool under the guidance of our industry-expert instructors.
You will learn how to
- Use Memory BIST concepts in the design process
- Understand Memory faults and algorithms for testing such faults
- Model memories for MBISTArchitect
- Generate Memory BIST logic for testing stand-alone or embedded memories
- Customize BIST Controller Hardware for Full-speed operation, Algorithm Selection etc.
- Diagnose memory failures using BIST logic
- Generating BISA Hardware
- Use MBISTArchitect to integrate BIST Hardware to SoC design
- Integrate BIST Controller to JTAG Controller
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Memory BIST software. Hands-on lab topics include:
- Creating a Basic Memory BIST Collar
- Verifying the BIST Circuitry
- Choose from Standard BIST Algorithms
- Changing the Data Background
- Inserting BIST for Multiple Memories
- Adding BIST with a Compressor
- Adding BIST for Bidirectional Memories
- Adding BIST for ROMs
- Running BIST at Full-Speed
- Inserting Diagnostic Hardware
- Injecting failure and scanning out diagnostic data (Default operation Restart Mechanism)
- Injecting failure and scanning out diagnostic data (With hold operation)
- Reviewing a User Defined Algorithm
- Running a User Defined Algorithm File
- Inserting BISA Hardware
- Inserting BISA Hardware for multiple memories
- Inserting online algorithm Selection Hardware
- Simulating online algorithm selection for BIST Simulation time reduction
- MBISTArchitect Flow Examples
- Controller/Collar top-level pin mapping
- Controller/Collar top-level pin sharing
- Integration of BIST and JTAG Controller
Audience
Designers, Design-for-Test Engineers and Test Consultants involved with creating testable ASIC's and IC's and producing the manufacturing test sets Traditional test engineers CAD engineers and managers CAD staff seeking to understand the effect of memory BIST on the design flow.
Prerequisites
- Experience with UNIX environments
- A background in DFT
- A basic understanding of memories and their structure
Key Topics
- Memory BIST concepts
- Advantages of adding BIST
- Memory testing and fault types
- Memory BIST algorithms
- March C
- Varying the data background
- Configuring memory BIST circuitry
- Support for multi-port memories
- Unique address
- ROM algorithm
- Port interaction test
- Generating a comparator functional test
- Inserting BIST for multiple memories
- Performing sequential memory tests
- Adding diagnostics
- Compressor vs. Comparator
- Adding pipeline registers
- Bypassing memory in scan mode
- Memory model syntax
- Understanding clocking schemes
- Defining memory ports
- Interpreting data sheets
- Defining read and write cycles
- Logical to physical mapping
- Descrambling functions
- User-Defined Algorithm
- Online Algorithm Selection
- Built-In-Self Analysis
- Creating and connecting BIST structures
- Validating a memory model
- BIST-JTAG Integration
- Top-Level Pin Mapping
- Top-Level Pin Sharing
- Controllers Scheduling
- Integrating BIST patterns
- Verification of BIST patterns