Design-for-Test: TestKompress
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Duration: 2 Days
Pricing: 3600 CNY
Course Part Number: 221302
Course Overview
This course introduces Embedded Deterministic Test (EDT™) technology and TestKompress™ to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with the Mentor Graphics DFT tool suite under the guidance of our industry-expert instructors.
You will learn how to
- Use TestKompress in three different IP generation flows
- Perform EDT Automation with TestKompress
- Create TestKompress patterns
- Perform At-speed testing
- Perform Modular TestKompress
- Use TestKompress and Boundary Scan in the same flow
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience in using TestKompress under the guidance of our expert instructors. Hands-on lab topics include:
- IP & Pattern Generation Flows
- IP Features and Options
- TestKompress Design Rule Checking (DRC)
- Troubleshoot DRC Violations (various K19)
- Compression and Performance
- At-speed Testing
- TestKompress and Boundary Scan
Audience
- Engineers with ASIC/IC/SOC design projects targeted at 130nm, and who are already familiar with the concepts of Design-for-Test.
- Engineers adopting at-speed test, or with pattern volume or test application time issues
- Designers, Design-for-Test Engineers and Test Consultants involved with creating testable ASICs and ICs and producing the manufacturing test sets
- Traditional test engineers
- CAD engineers and managers
- CAD staff seeking to understand the effect of EDT on the design flow
Prerequisites
- Experience with UNIX environments
- A background in DFT (Design-for-Test)
- Mentor Graphics Education Services training course, Design-for-Test: ATPG Training
Key Topics
- Traditional IC Test Methods
- Current Design Trends
- Different Kinds of Defects
- Solution to Current Trends: Complete Testing
- At-Speed Testing Requirements
- Embedded Deterministic Test (EDT)
- Data Volume and Test Application Time
- ATPG with Standard Scan
- ATPG with EDT
- Standard Scan Test Application Process
- EDT Test Application Process
- Advantages of Embedded Deterministic Test
- TestKompress Flow and Usage
- TestKompress IP Creation
- TestKompress Pattern Generation
- TestKompress Design Rule Checking (DRC)
- TestKompress "K" Rules
- Pattern Simulation Mismatch and Debugging
- Saving Pattern Files for Simulation Mismatch Debugging
- Maximizing, Evaluating, and Improving Performance
- Modular TestKompress
- Full-Flow Design-for-Test (DFT)