ASIC Design Kit

ASIC Design Kit 3.1 Now Available

The ASIC Design Kit (ADK) is a generic design kit providing all the requisite data, libraries, and documentation to create ASIC designs using the Mentor Graphics suite of layout, synthesis, simulation, and DFT tools. Its primary use is by universities and colleges in class work environments.

The target technologies are AMI 0.5m and 1.2m and TSMC 0.35m, 0.25m and 0.18m.

The kit provides:

• Support for schematic, HDL or mixed schematic/HDL based designs
• Synthesis support for Leonardo Spectrum
• Pre-layout timing simulations with ModelSim (VHDL or Verilog)
• Scan insertion support for DFTAdvisor
• Automatic test pattern generation support for FastScan or FlexTest
• Static timing analysis models for SST Velocity
• Automatic place and route of designs using IC Station
• Post-layout timing simulations with ModelSim (VHDL/Verilog), MachTA, or Eldo
• Support for DA-IC

Register and Download ASIC Design Kit 3.1

1. Please refer to the:

• Documentation and Tutorials
• Questions & Issues

2. For Mentor Graphics tool specific issues when using the ADK, please contact your local Mentor Graphics Support Hotline.

3. For specific ASIC Design Kit issues, please email higher_education@mentor.com