CMOS IC LAYOUT Guide to Topological Chip Design

Author: William Bradbury, EduMedia Development, Corp.

A student version of Mentor Graphics’ IC Station for Linux is included on an accompanying CD. All examples and exercises are tested and validated with both the student and full production versions of IC Station.

For more information on this book, including ordering information, please visit EduMedia Development Corp

Introduction

CMOS IC Layout: A Guide to Topological Chip Design is designed to guide you to an intermediate-level understanding of the actual processes used in generating a topological layout for a CMOS-integrated circuit.

To accomplish this, the text will walk you through the major steps in the IC development flow, layout floor planning, converting design engineering’s logic diagrams into transistor schematics, cell layout, how to build and use a standard cell library, and interconnect techniques. This is followed by descriptions of the processes that follow the layout through to the finished product, including layout verification and a minimum area layout affects yield. Additionally, through out the book. Designing in reliability is stressed and the consequences of not adhering to good layout practices are shown graphically with scanning electron microscope photos to carry the point home.