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Building the System-in-Package Design Infrastructure


December 2006

Advanced Design, Partitioning and Test for System-in-Package Electronics (ADEPT-SiP)

The new System-in-Package (SiP) paradigm in electronics product implementation allows the mixing of optimum active and passive device technologies in bare die format within a single package outline for cost effective, high performance, short time-to-market functionality well matched to a wide range of low, medium and high volume electronics product applications. The novel addition of embedded passive component technology within such SiP modules also promises further performance, size, weight and cost benefits.

The SiP approach allows board level functionality to be realised at the package level for smaller, lighter and higher functionality products. However a major obstacle to the successful introduction of this new technology is the lack of a robust design methodology supported by rigorous simulation tools, accurate component and technology models. The ADEPT-SiP project, that is funded through the DTI Technology Programme under the Design, Simulation and Modelling Technology priority area, is directed at eliminating this obstacle.

The 30-month ADEPT-SiP project started in May 2006 and will develop and demonstrate a rigorous, right-first-time design and supply chain management methodology for novel System-in-Package Electronics Product Functions. It will address schematic capture, partitioning and active device, substrate and package design to meet specific performance, cost, size and weight targets. Other key design stages will include thermal and EMC design, and design-for-manufacture, for test, reliability and for environmental impact. Novel, high density embedded passive substrate technologies will be designed and simulated, process characterisation undertaken and component models developed for the full range of passive components and interconnection and assembly structures. The core design, simulation and modelling activities will then be proven in SiP technology demonstrators.

The ADEPT-SiP project partners include Filtronic Broadband and Zarlink Semiconductors' Advanced Packaging Division based in Caldicot as SiP product end-users, Leeds University as modelling provider, Zuken, QuantumCAD and Flomerics as design providers, and Wurth Elektronik and TWI as technology providers. Further information on the ADEPT-SiP project may be obtained from the project web site, www.adept-sip.com.

David J. Pedder, M.A. (Cantab.), Ph.D.,
ADEPT-SiP Project Manager
TWI Ltd., Granta Park, Great Abington,
Cambridge CB1 6AL, UK
Tel: +44 1223 899000 (switchboard)
Tel: +44 1223 899512 (direct)
Mobile: +44 (0)7899 952230
e-mail: david.pedder@twi.co.uk

For further information, please contact:

Nazita Saye
Head of Marketing
Mentor Graphics Mechanical Analysis, UK
81 Bridge Road
Hampton Court
Surrey, KT8 9HH
UK

Tel: +44 (0)20 8487 3000
Fax: +44 (0)20 8487 3001

 
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