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Mentor Graphics Calibre Tools Strengthen DFM Flow for IBM/Chartered/Samsung 65 nm Common Platform Technology

WILSONVILLE, Ore., March 30, 2006 - Mentor Graphics Corporation (Nasdaq: MENT) today announced that several best-in-class tools from the Calibre{reg} design-to-silicon platform are qualified and available to support a robust Design for Manufacturing (DFM) methodology for the IBM/Chartered/Samsung 65-nanometer (nm) process Common Platform technology. These production-proven tools further empower designers targeting the cross-foundry process to identify and address possible yield detractors early in the design flow, thereby improving the likelihood of successful yield in leading-edge nanometer technologies. Flexible foundry support for this new breed of DFM tools is imperative for the success of next generation IC design flows.

More specifically, Calibre LFD™ is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation. Calibre LFD enables designers to make trade-off decisions on how to create a design that is more robust and less sensitive to the lithographic process window. This is important at the 90-nm technology node, and crucial at the 65-nm node, where even small process variations can greatly influence silicon results. An LFD kit is provided to the designer by the Common Platform manufacturing partners and is useable to target the common 65-nm process from any of the three manufacturing facilities, much in the same manner as a design rule checking (DRC) kit. The encrypted kit includes energy, dose and mask bias considerations; RET recipes, process models, and the parameterizable rules to be checked. The designer can run simulations to see how a layout will perform under a particular lithographic process window. The goal is to drive the design to an "LFD clean" as well as a "DRC clean" sign-off.

"IBM, Chartered and Samsung have worked closely with Mentor in the optimization of Calibre LFD for the Common Platform technology at 65nm," said Steve Longoria, vice president, Semiconductor Technology Platform for IBM Systems and Technology Group. "The availability of this tool enhances our platform DFM suite and expands our open ecosystem based on collaboration and innovation. Design teams can explore lithographic sensitivities early in the design stages, and make critical decisions before the design is sent to fabrication in any of the three partners' respective facilities."

Calibre YieldAnalyzer™ provides a comprehensive approach for the Common Platform to deliver a design-for-yield capability to customers. Calibre YieldAnalyzer includes DFM rules that cover all key areas of yield loss such as random, systematic and parametric. The Common Platform leads the industry in providing yield improvement metrics that show designers how and where they should spend their time to improve the yield of their designs. The Common Platform uses the power of YieldAnalyzer to deliver their yield improvement metrics to customers in the form of a Calibre DFM deck, which provides designers a natural extension of DRC with DFM.

"The volume and complexity of 'sign off' rules at 65 nanometers is staggering," said Ana Hunter, vice president of technology for Samsung Semiconductor, Inc. "This daunting task can be simplified and, through our cooperative efforts designers are empowered to evaluate trade offs, and get a relative idea of how each decision impacts yield themselves."

"Today, we've reached a major milestone in the adoption of new tools and technologies that address DFM, and we are pleased to be supporting the Common Platform model as a viable option for our customers," said Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "The infrastructure to manage the analysis and prevention of yield loss mechanisms is taking shape, and proving itself to be extremely valuable."

About Common Platform DFM Strategy

The Common Platform partners outlined their DFM strategy and roadmap in September 2005, highlighting the eight key areas of focus by the joint development teams. The collaborative effort addresses pressing design closure challenges, including timing, area, power, signal integrity, and manufacturability. The DFM capabilities are delivered through a series of rules- and model-based design kits that contain critical information required by designers to better predict the impact their decisions will have on a manufactured designs implemented in a variety of operating ranges, modes, and conditions. The capabilities from the EDA and DFM suppliers benefit from a rigorous qualification process in all three companies' manufacturing environments, as well as the system-level design expertise the Common Platform partners bring with respect to DFM.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.

Mentor Graphics and Calibre are registered trademarks, and Calibre LFD and Calibre YieldAnalyzer are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information, please contact:

Carole Thurman
Mentor Graphics
503.685.4716
carole_thurman@mentor.com

Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com

 
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