Mentor Graphics Extends Catapult C with Support for Control Logic to Enable Full-Chip High-Level Synthesis
WILSONVILLE, Ore., June 29, 2009 – Mentor Graphics Corp. (NASDAQ: MENT), the market and technology leader in high-level synthesis solutions, today announced that the Catapult® C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS). This breakthrough technology allows designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. Extending the Catapult C tool’s capabilities to full-chip high-level synthesis is critical due to the rapid growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.
Control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool unifies these two domains, allowing users to describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++. At the heart of this innovation is a new synthesizable C++ construct, which allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation. This pivotal mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks. The result is a coding style familiar to hardware designers, letting users easily express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.
The synthesis process is complemented by a patent-pending and fully automated verification flow which for the first time lets users validate the detailed RTL-level block interactions at the C level. Tight integration between verification and synthesis has proved a necessity to realizing the full potential of HLS. A common pitfall found with other HLS tools is developing high-level synthesis in isolation, which results in overly complex verification of the RTL output.
"Our digital broadcasting ICs typically consist of a complex mix of compute intensive algorithmic units and control dominated blocks," said Professor Schlicht, Head of Department, Fraunhofer Institute for Integrated Circuits. "The new Catapult extensions for control-logic synthesis provide us with the capability to develop an increasing portion of the overall system using high-level synthesis from C++. This allows us to extend our C++ based implementation flow beyond the pure signal processing blocks."
In addition to support for control logic, the Catapult C Synthesis tool has added innovative technology for low power design by automating two prevailing design techniques: multi-level clock gating and interfacing to dynamic power and clock management units. The Catapult C tool will analyze deep cones of logic to find gateable clocks, an otherwise error-prone and manual task typically done by backend low power experts. This new and unique optimization delivers near 100% perfect clock gating by operating at the flop level, maximizing power savings by locally inferring the gating logic surrounding the targeted registers. To help further reduce power, the Catapult C Synthesis tool also exports real-time information on the state of all system blocks. This information is relayed to power management units leveraging dynamic frequency and voltage scaling heuristics to achieve system-wide power savings. As expected, dynamic power savings is design and test vector dependent; measurements on more than 300 customer designs showed improvements ranging from 10 to 90%, with an average improvement of 40%. "The control logic extensions of Catapult C now let us develop a larger part of our systems with HLS," said Emmanuel Liegeon, Deputy Manager of Digital ASIC & FPGA Design Group, Thales Alenia Space. "As we develop more and more of the system in HLS, it becomes paramount to get power right. The latest enhancements in Catapult C for low power are delivering the optimizations we need."
The Catapult C Synthesis tool is the first product to automatically generate control and algorithmic RTL multi-block designs from a pure ANSI C++ source where both the core algorithm and interface are untimed. This productivity improvement gives designers time and freedom to automatically perform detailed design exploration of different micro-architectural options and interface scenarios to quickly achieve fully optimized hardware designs.
The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000. For more product information on the Catapult C tool, contact your Mentor Graphics sales representative, call 1-800-547-3000, or visit the website at http://www.mentor.com/products/esl/catapult-c
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
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