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Cypress Adopts Mentor Graphics Calibre xRC For Parasitic Extraction; Cites “Unparalleled Accuracy”

WILSONVILLE, Ore., Dec. 14, 2006 - Mentor Graphics Corporation (Nasdaq: MENT) today announced that its high-performance parasitic extraction solution, Calibre® xRC, is being used by Cypress Semiconductor Corp. in production flows for 130-, 90- and 65-nanometer processes. Calibre xRC was used at Cypress on the industry’s first 72 Mb SRAM, as well as other custom memory, microcontroller and clock designs. Calibre xRC was chosen for its demonstrated accuracy in analog/mixed-signal ICs, and an open calibration flow that accommodates internal manufacturing processes.

“Our latest PSoC® designs are targeted at nanometer process nodes requiring very accurate parasitic extraction to feed into our downstream simulation,” said Andy Hawkins, vice president of Design Technology at Cypress. “Additionally, because many of our designs are mixed-signal, the combination of analog and digital content requires a mixed methodology of flat and gate-level extraction.”

Calibre xRC is part of Mentor’s market-leading Calibre design-to-silicon platform. Cypress also uses Mentor’s physical verification tools, Calibre nmDRC (design rule checking) and Calibre LVS (layout vs. schematic), as the internal sign-off standard, and Calibre OPC (optical and process correction) technology for resolution enhancement.

“For nanometer designs, accurate simulation and analysis requires more than traditional resistance and capacitance. Designers need a post-layout silicon model that incorporates inductance, in-die variation effects, and efficient accounting of effects not captured in the device model.” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “Calibre ensures that designers have all the data they need to obtain successful first pass silicon.”

Enabling Accurate Post-layout Functional Verification: The New Nanometer Silicon Model
Shrinking geometries and increasing design size in the nanometer era have enabled greater functionality on a single chip. But with the increased functionality comes new complexities that create more problems in the attempt to attain design closure. This requires an electrical representation of the chip that accounts for the actual physical design of its devices and interconnect; an accurate silicon model. Calibre xRC meets the demands of nanometer designs with a comprehensive approach to device and parasitic extraction to compose accurate silicon models enabling a large variety of post-layout analyses.

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $750 million and employs approximately 4,100 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information, please contact:
Carole Thurman
Mentor Graphics
503.685.4716
carole_thurman@mentor.com

Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com

 
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