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Mentor Graphics Design-for-Test Team Awarded IEEE CEDA Donald O. Pederson Best Paper Award

WILSONVILLE, Ore., July 12, 2006 – Mentor Graphics Corporation (Nasdaq: MENT) today announced that a team from its Design-for-Test (DFT) Division has been awarded the prestigious 2006 IEEE Circuits and Systems Society Donald O. Pederson Best Paper Award. The award, given for the team’s ground-breaking work on Embedded Deterministic Test (EDTtm), honors the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The DFT team: Janusz Rajski, Jerzy Tyszer, Mark Kassab and Nilanjan Mukherjee, developed the EDT technology to provide a significant reduction in scan test data volume and scan test time. The new technology is composed of two complimentary parts: hardware that is embedded on chip, and new deterministic ATPG methods that generate highly compressed patterns that utilize the embedded hardware.

The patented EDT technology was commercialized in 2001 with the introduction of TestKompress{reg}, the industry’s first embedded compression tool. Since its introduction, TestKompress has been used in the design of hundreds of semiconductor products including processors, communications devices, automotive electronics and consumer products. It’s estimated that EDT patterns have tested over a billion devices worldwide in the five years that TestKompress has been on the market.

“This award is an excellent example of the continuous innovation that has been taking place at Mentor Graphics over the last 25 years,” said Robert Hum, vice president and general manager of the Design Verification and Test Division of Mentor Graphics. “Breakthrough innovation of this kind moves the state of the art in the industry forward to solve the serious test challenges presented at the deep submicron level.”

Janusz Rajski will be presenting the work as part of the distinguished speaker series at the Design Automation Conference in San Francisco on July 24th at 5:30pm. This will be the second TCAD Best Paper Award for Dr. Rajski, who also received one with Jagadeesh Vasudevamurthy in 1993 for their breakthrough work on logic synthesis.

IEEE CEDA Donald O. Pederson Award
The IEEE CEDA Donald O. Pederson Award is named in honor of Don Pederson who was a faculty member of the UC Berkeley Department of Electrical Engineering where he served as the director of the Electronics Research Laboratory and chairman of the Department of Electrical Engineering and Computer Sciences.

Pederson received numerous awards throughout his career and in 1998 he was awarded the IEEE Medal of Honor, the Institute's highest award, "for the creation of the SPICE Program, universally used for the computer aided design of circuits." Pederson was a co-founder of the IEEE Solid-State Circuits Council, the forerunner of today’s Solid-State Circuits Society, in 1966, and he was instrumental in launching the IEEE Journal of Solid-State Circuits that same year.

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/

Mentor Graphics and TestKompress are registered trademarks, and EDT is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information, please contact:
Carole Thurman
Mentor Graphics
503.685.4716
carole_thurman@mentor.com

Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com

 
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