Mentor Graphics Underscores Low-Power Strategy with Vista Architecture-Level Power Solution
Power modeling, analysis and optimization at the transaction level
DESIGN AUTOMATION CONFERENCE, San Francisco, Calif., July 27, 2009 - Mentor Graphics Corporation (NASDAQ: MENT) today emphasized its low-power strategy with the announcement of its fifth product platform this year with major new capabilities addressing low-power issues. The Mentor Graphics® Vista™ platform, for comprehensive architecture design and prototyping, now allows users to model, analyze and optimize power at the transaction level of abstraction. The Vista product joins other Mentor® products, including the Catapult® C high-level synthesis tool, the Questa® advanced functional verification platform, the Olympus-SoC™ place and route platform, and the HyperLynx® PI power analysis tools, that together provide an end-to-end solution for low-power design, verification and implementation.
“Low power has become a main differentiator for the design of electronic systems,” said Walden C. Rhines, chairman and CEO, Mentor Graphics. “Mentor’s low power strategy is to address power minimization on the total system at every stage of the design and verification flow, offering the most comprehensive suite of low power technologies so customers can implement precisely what they need.”
The Vista Platform
The Vista platform enables engineers to model power at the transaction architecture level using advanced power estimation policies long before an implementation becomes available, or annotate more accurate power behavior based on attributes of the technology process of the target implementation IP blocks.
“Because our storage solutions are complex by nature, it is critical we understand the system requirements and capabilities before we choose a system architecture,” said Terry Doherty, engineer at Emulex. “Using Mentor’s Vista platform, we are able to model the system architecture early in the design process, quantify the system performance and identify architectural limitations. This allows us to get to an optimal system architecture quickly while meeting solution requirements. Without this level of analysis we would not have been able to predict system performance until the system was fielded.”
The Mentor Vista platform of low-power electronic system level (ESL) design tools provides a “layered” behavioral, timing and power modeling design methodology coupled with the SystemC Transaction-level Modeling Standard (TLM-2.0) supported by the Open SystemC Initiative (OSCI). Vista offers an advanced design platform that allows chip designers and system architects to make viable decisions on hardware/software partitioning and architecture structures. With its advanced debug and analysis toolset, users can verify system-wide functionality, analyze and optimize systems under realistic traffic loads, and adjust system resources for optimal performance and power. Users can also explore various voltage scaling and shutdown techniques and apply the most efficient power management strategies.
As a result, designers can ensure a cost-effective architecture with a suitable bandwidth that can carry the target application. Given the abstraction and fast simulation of the hardware representation, a model of the system can then be used as a virtual platform for early software development, analysis and validation, including the ability to profile power while executing application software.
“Power has become one of the most pressing constraints in current applications,” said Guy Moshe, general manager and director of Mentor Graphics ESL/HDL design creation division. “We believe that managing power at the very early design stage, and way ahead of implementation, can offer high-value to our customers in their efforts to better differentiate their products while producing low-power devices.”
About Mentor's ESL Design Tools
Mentor provides an industry leading ESL design flow that spans from architecture-level design and prototyping using Vista to high-level synthesis using Catapult C. Mentor's ESL flow allows chip designers and system architects to optimize multi-core platforms for performance and power, delivers a virtual platform of the hardware to the software team early in the process and efficiently synthesizes high-level IP descriptions into RTL. Mentor's ESL solution is based on a scalable design methodology and market standards, and is tightly coupled with RTL design and verification flows.
The Vista platform is available for deployment at customer sites, effective immediately, and pricing begins at $100K. For more product information on the Vista Platform, contact your Mentor sales representative, call 1-800-547-3000, or visit the website at http://www.mentor.com/esl
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics, Mentor, Questa, Hyperlynx and Catapult are registered trademarks, and Vista and Olympus-SoC are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)
For more information, please contact: