Hitachi Employs Mentor Graphics Olympus-SoC Place and Route Platform for Critical ASIC Designs
WILSONVILLE, Ore., June 5, 2012 — Mentor Graphics Corp. (NASDAQ: MENT) today announced that Hitachi, Ltd. (Chiyoda-ku, Tokyo) has adopted the Olympus-SoC™ place and route system for large scale ASIC development, and has achieved successful tape out of a 40nm, 90 million gate design.
“Hitachi was able to easily close timing for this large scale 90 million gate design using the large flat mode capacity of Olympus-SoC,” said Kazuhisa Miyamoto, senior director, MONOZUKURI Innovation Group, Hardware MONOZUKURI Division, Information & Telecommunication Systems Company, Information & Telecommunication Systems Group, Hitachi, Ltd. “Not only did Olympus make it easier and faster to close the design, but we also got much better quality of results. Through good communication with R&D, Mentor Graphics provided us with swift support whenever we got into trouble. We believe it is truly significant for our business that we completed such a successful tape out with Olympus-SoC.”
The Olympus-SoC place and route platform features a unique, patented architecture specifically created to address extremely large and complex IC designs. Olympus-SoC has a very compact database that enables it to handle full-chip designs with hundreds of millions of gates in flat mode. This, combined with native multi-corner, multi-mode optimization, provides improved timing and signal integrity for chips with exploding gate counts and mode-corner scenarios. The system also provides full support for multi-voltage, low-power designs including advanced algorithms for clock tree optimization and leakage reduction. The Olympus-SoC router has also been architected to handle complex design rule checking (DRC) and design for manufacturing (DFM) requirements for advanced process nodes, including pattern matching, and priority-based recommended rules support. The Olympus-SoC system is tightly integrated with the Calibre® verification and design for manufacturing (DFM) platform to address manufacturing variability with signoff verification at the design stage.
“Many place and route tools based on older architectures are out of steam at 40nm and 28nm, where designers face 100M gate design complexity along with high performance and low power challenges,” said Pravin Madhani, general manager of the Place and Route group at Mentor Graphics. “The Olympus-SoC architecture is built to address the capacity, performance and low-power requirements of smaller geometry nodes. Olympus-SoC also has tight links with Calibre, enabling designers to create “first time right” designs that meet all the signoff requirements of the target foundry without costly design iterations.”
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of about $1,015 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.
(Mentor Graphics and Calibre are registered trademarks and Olympus-SoC is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)