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Renesas Reduces Cost, Improves Quality with Mentor Graphics Hybrid TestKompress/LogicBIST Solution

For more information contact

Sonia Harrison
sonia_harrison@mentor.com
Mentor Graphics
503.685.1165

Gene Forte
gene_forte@mentor.com
Mentor Graphics
503.685.1193

WILSONVILLE, Ore., September 10, 2013 - Mentor Graphics Corp. (NASDAQ: MENT) today announced that Renesas Electronics is using the Tessent® Hybrid TestKompress®/LogicBIST solution to address safety critical test requirements defined by the ISO 26262 standard. The hybrid technique requires significantly less test logic to provide a complete solution including both high-compression scan test for low defects per million (DPM), and built-in self-test (BIST). Mentor’s hybrid test capability is ideal for high-reliability applications in the automotive and other industries.

“The combination of compressed scan test and logic BIST gives Renesas a high-quality solution for both production test and Power-On Self-Test, which is required by the ISO 26262 standard in the automotive industry,” said Toshiharu Asaka, chief professional of the Design Automation Department, System Integration Business Division at Renesas Electronics Corporation. “By adopting Mentor’s integrated solution rather than separate ATPG compression and BIST implementations, Renesas further simplifies its DFT implementation flow, which reduces the die area needed for test logic, saves developer time, and accelerates time-to-market.”

The Tessent Hybrid TestKompress/LogicBIST solution delivers in-the-field system self-test complemented by compressed ATPG to achieve the highest test quality, even where the tester memory and interface are limited, such as during burn-in test. The solution generates LBIST logic integrated with embedded compression logic, and automatically generates targeted “top up” patterns compressed by 100X or more to complement the LBIST pseudorandom patterns. The hybrid solution can reduce production test time and cost, while delivering low DPM and an in-system test capability.

“The Tessent hybrid methodology is one of the most effective ways to reduce test cost and test time for IC products that require very thorough testing on the production line, as well as self-test capabilities after being placed into service,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “As a bonus, designers also save on the amount of logic required to implement these test functions and also enjoy a simplified implementation process.”

(Mentor Graphics and Tessent are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

 
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