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Mentor Graphics Questa CDC Adopted by iD Corporation for Clock Domain Crossing Verification Signoff

For more information contact

Carole Dunn
carole_dunn@mentor.com
Mentor Graphics
503-685-4716

Ry Schwark
ry_schwark@mentor.com
Mentor Graphics
503.685.1660

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Questa® CDC Verification

The Questa Clock-Domain Crossing (CDC) Verification solution focuses on the interaction between these clock domains. Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques. Learn More

WILSONVILLE, Ore., August 21, 2012—Mentor Graphics Corp. (NASDAQ: MENT) today announced that iD Corporation has selected Questa® CDC for clock domain crossing verification of their complex SoC and FPGA designs. iD Corporation, which develops ICs for network and wireless communications, adopted Questa CDC as their standard design methodology to improve both design quality and design schedule predictability. Questa CDC has enabled iD to achieve successful tapeouts of very large scale SoC designs, up to 90M gates in size, with many asynchronous clocks.

“We are extremely pleased that with Questa CDC, we have eliminated the risks of project delay and silicon re-spin due to asynchronous clock crossings,” said Koetsu Narisawa, vice president, Hardware Development, iD Corporation. “With Questa CDC, we now find CDC problems early in the development phase, before simulation, and avoid the time consuming process of debugging these issues in hardware. Key attributes of Questa CDC, such as its comprehensive analysis and its intuitive visualization of CDC results, prompted us to adopt the Questa CDC methodology for all of our SoC and FPGA designs.”

As developers of state-of-the-art designs for networking devices, iD’s design teams are faced with the two-fold challenge of increased design complexity and shrinking time-to-market windows. The vast majority of today’s SoC and FPGA designs contain multiple asynchronous clocks and companies such as iD need a comprehensive solution for CDC verification. Using Questa CDC’s static analysis capabilities, iD’s design teams can quickly and easily uncover bugs in asynchronous circuits and avoid discovering them late in the design cycle or during lab verification.

Questa CDC is used extensively by leading semiconductor design teams and sets the bar for capacity, ease of use and quality of results. Across the industry, Questa CDC is widely used as the gold-standard for CDC-signoff checking before tapeout, and its versatility enables it to be deployed across the full range of designs from SoCs to FPGAs allowing for a consistent, company-wide methodology.

“iD is indicative of the trend we see with progressive design companies across the industry who have standardized on Questa CDC,” said Roger Sabbagh, product marketing manager, Questa Static Verification, Mentor Graphics. “Questa CDC gives companies such as iD the confidence to tapeout designs with even the most demanding CDC verification requirements.”

(Mentor Graphics and Questa are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

 
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