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Mentor Graphics and Samsung Optimize 14nm Process Design Kits

WILSONVILLE, Ore., May 31, 2013—Mentor Graphics Corp. (NASDAQ: MENT today announced that Calibre® nmDRC™ and Calibre nmLVS rule decks for Samsung’s 14nm IC manufacturing processes have been significantly improved since first release. For example, the joint efforts have resulted in a 50% better performance over the previous release for the Calibre nmDRC design kit. The revised decks provide rapid turnaround and also reduce customers’ datacenter costs by reducing compute platform memory requirements. While cycle time is important for every process node, with the significant increase in design sizes at 14nm, continuous performance optimization of verification run times is especially critical.

“Samsung and Mentor are working closely to ensure that Calibre signoff results are both accurate and available when needed by our mutual customers,” said Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Samsung Electronics. “We use the Calibre platform as the reference tool for our design rule manual (DRM) verification, so the Calibre decks are the first ones available to our customers. Our customers need both accurate signoff to make sure their designs are ready for manufacturing, and continuously improving performance to minimize their design cycle time.”

In other collaborative efforts, Mentor and Samsung recently completed the 14nm rule deck development for the Mentor® Olympus-SoC™ place and route system, and the Olympus-SoC product was used to create a 14nm test chip with critical routing patterns for large differentiating IP blocks with representative libraries, via stack configurations, and other key parameters. Samsung has also released a 14nm process design kit for the Calibre LFD™ (Litho Friendly Design) product with specific coaching on the elimination of DFM litho errors to make fixing violations faster and more accurate.

“We engage with Samsung at the earliest stages of process qualification and work right on through to volume production at each process node,” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “There are many opportunities to add value for our mutual customers as we fine tune the design flow for better functionality, higher accuracy and faster performance.”

(Mentor Graphics, Mentor and Calibre are registered trademarks, and nmDRC, Olympus-SoC and LFD are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

For more information

Sonia Harrison
Mentor Graphics

Gene Forte
Mentor Graphics

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The Olympus-SoC™ physical implementation platform meets the highest demands of IC designs at advanced nodes. Learn More

Calibre nmLVS™, the industry-leading physical verification tool combines accurate circuit verification with fast runtimes & interactive debugging. Learn More

Calibre nmDRC™, the industry-leading for design rule checking provides fast cycle times and innovative design rule capabilities. Learn More

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

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