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Mentor In The News
Mentor In The News
Q2 2006
Mentor Graphics Honored with Ethics Award
Q4 2005
SystemVerilog Approved as IEEE Standard
Q3 2005
What's Hot in Assertion-Based Verification?
DFT drives yield improvement
Q2 2005
Formal Verification with ABV Made Practical
Support drives SystemVerilog
Choosing the Right FPGA Design Tools - EDA Alert, contributed by Simon Bloch
FPGA Design Needs More Than a Face Lift
Q1 2005
Step 1: Design for Manufacture - SMT, Contributed article by Charles Pfeil
Q4 2004
A practical view of ESL design - EEdesign
IP reuse simplifies SoC design, verification - EE Times, Contributed article by John Wilson
Good bridge testing needed - EE Times, contributed article by Greg Aldrich and Brady Benware
Smart test for nanometer designs - Test & Measurement World, contributed article by Ron Press
Q3 2004
Platform-Based Design and Verification with Automated IP Integration - EE Times
Riding High on Change - Electronic News
Mentor Graphics Chief Looks to New Challenges - Test & Measurement World
Static verification needs a parallel approach - EE Design (contributed)
Rhines: DFM best bet for EDA growth - EE Times
Q2 2004
Book can help you with FPGA designs
An Integrated Approach to Designing-in FPGAs - Printed Circuit Design & Manufacture (contributed)
The Advanced Technology Winner: A Toolset Provider Perspective - SurfaceMountTechnology
What's Yield Got to do with IC Design - EE Design (Contributed)
Mentor FPGA synthesis users speak out - EE Times
Q1 2004
EDA revenues jump in fourth quarter of 2003 - EE Times
A new vision of 'scalable' verification - EE Design (contributed)
UK engineer wins worldwide design competition - EE times UK
EDA Market Shows New Strength - Electronic News
Mentor Graphics Announces Winners of Its 18th Annual PCB Technology Leadership Awards - DACafe
Special Market Focus: Chipd Design Alternatives - Electronic News
Mentor expands Chinese university program - EE Times
ARM7 and Nucleus RTOS on Tour with Paul McCartney - IQ Magazine (contributed article)
Silicon modeling in the nanometer era - EE Times (contributed)
EDA CEOs field provocative questions - EE Times
Vendors make progress on Verilog 2001 compliance - EE Times
Juggling jobs: hardware/software co-design - EDN (incl. sidebar)
Accellera chairman's message: 'screw standards' - EE Times
Tool tackles complex FPGAs - EDN
VHDL does not need the "System" moniker - EDN (contributed sidebar )
Mentor upgrades analog mixed signal - EE Times
Put "free" silicon to work - Test & Measurement World (contributed)
Lithography: The Integration of TCAD and EDA - Semiconductor International (contributed)
Mentor Graphics Has Hand in Intel's Grantsdale - Electronic News
Mentor readies PCB tools for Intel "Grantsdale" chip set - EE Times
Research park at USA offers students new experiences and relationships - Vanguard, University of Alabama
Emulation on the Cheap - ASIC prototyping with FPGAs - FPGA Journal
What you lose from a lossy line - EDN (contributed)
Physics Drives Physical into the Mainstream - FPGA Journal
Mentor Receives Chartered Semiconductor Silver Services Supplier Awards
Mentor's Rhines sees a robust, long recovery - The Portland Business Journal
Mentor Hits Record Revs - Electronic News
Mentor's Calibre tool licenses lead to boom quarter - EE Times
Mentor Q4 suggests selective EDA recovery - EE Design
Mentor's fourth quarter to show higher sales, lower earnings - Portland Business Journal
GDSII-based flow speeds mask data preparation - EE Design (contributed)
Step 1: Design for Manufacture - SMT (contributed)
