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Mentor Graphics Provides Advanced Design For Manufacturing Capabilities in TSMC Reference Flow 9.0

WILSONVILLE, Ore.– June 12, 2008 – Mentor Graphics Corporation (Nasdaq: MENT) today announced that Mentor’s place-and-route, physical verification, design-for-manufacturing (DFM) and design-for-test (DFT) tools can be accessed through Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) Reference Flow 9.0.

“Mentor Graphics continues to address the growing challenges of advanced IC design and manufacturing,” said S.T. Juang, senior director of design infrastructure marketing at TSMC.

TSMC Reference Flow 9.0 accesses Mentor capabilities in the following areas:

  • New DFM implementation capabilities for hierarchical critical area analysis (CAA), hierarchical chemical-mechanical polishing (CMP), concurrent CAA optimization
  • Hierarchical DFM analysis for all three physical DFM defects: lithography process checking (LPC), CMP and CAA
  • Electrical DFM improvements including Table-Based DFM-LPE (advanced device parameter) extraction, and Thickness-to-Electrical (T2E) silicon-based models
  • CMP support for E-Hotspots and intelligent metal fill with model- and density-based modes
  • DFT solutions addressing bridge defects with N-detection algorithms, and a layout viewer to show the physical location of defects
  • Memory built-in self-test (BIST) support for TSMC electrical fuse intellectual property (IP) for single-insertion embedded memory repair

“Our continued collaboration with TSMC is solving some of the biggest challenges for customers working at leading-edge process nodes,” said Joe Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. “Our close cooperation under TSMC’s Active Accuracy Assurance initiative means that Mentor design-to-silicon flows accurately reflect TSMC’s advanced manufacturing processes.”

Mentor’s Olympus-SoC system provides new capabilities for hierarchical CAA, hierarchical VCMP and concurrent CAA optimization. Using a variety of enhancement techniques such as cell swapping, via reduction, via doubling, expand enclosure, and wire spreading/widening, all within a timing analysis context, the Olympus-SoC system improves yield while ensuring rapid timing closure. The Olympus-SoC product also takes into consideration the density maps of cell libraries and macros during fill insertion for a more uniform fill.

The Calibre CMPAnalyzer model-based CMP solution, which has been certified since RF7.0 and extended with SmartFill in RF8.0, now supports T2E and E-Hotspots functionality. This provides thickness values at a higher resolution for CMP analysis, allowing both functional and electrical planarity analysis and control, and can drive more accurate parasitic extraction using the Calibre xRC™ product. Additionally, Calibre the nmLVS product has been enhanced to incorporate TSMC’s Table-Based DFM-LPE requirements for executing advanced device parameter extraction to account for silicon stress effects and provide the most accurate representation of manufactured devices.

The Calibre® YieldAnalyzer solution adds to Reference Flow 7.0 and 8.0 certification with hierarchical CAA for Reference Flow 9.0. It can characterize standard cells in terms of expected yield, and can be used with the Calibre YieldEnhancer tool for interactive IP fixing based on Critical Feature Analysis using recommended rules. The Calibre YieldAnalyzer product can also be used in a flow with the Olympus-SoC system by providing cell library yield assessment data, which the Olympus-SoC tool uses for cell selection. TSMC customers now have a complete solution for reducing random defects.

The Calibre LFD™ solution has been qualified for RF 9.0 as well as TSMC’s 4N40 processes for all layers, and now includes hierarchical LPC features for faster turn around time.

DFT capabilities based on the industry-leading TestKompress® scan test tool, MBISTArchitect™, and YieldAssist™ products, which have been part of TSMC’s reference flow since release 6.0, continue to include logic and memory testing, power reporting during automatic test program generation (ATPG) for addressing test-specific power issues, and timing-aware ATPG features for targeting small delay defects. In RF 9.0, the TestKompress product adds the ability to target bridge defects using N-detection algorithms. Mentor’s MBISTArchitect™ tool now provides support for TSMC embedded memories using the TSMC electrical fuse IP to enable single-insertion embedded memory repair during testing. Also, failure diagnostic capabilities have been enhanced by integrating the Mentor YieldAssist™ tool with the Calibre Layout Viewer to provide a physical layout view of defect areas.

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $850 million and employs approximately 4,200 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics, Calibre, and TestKompress are registered trademarks and LFD, Olympus-SoC, xRC, and MBISTArchitect are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

For more information, please contact:
Gene Forte
Mentor Graphics
503.685.1193
gene_forte@mentor.com

Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com