Circuit Semantics™ Inc.

DynaCell™, DynaCore™, DynaModel™, DynaTest™

Cell and block characterization, static timing analysis and functional modeling

Product Description

DynaCell - An automated characterization and validation system for standard cell libraries, IOs, and custom cells, for synthesis and custom design methodologies
DynaCell is a characterization tool for standard cell libraries, IOs, and custom cells. Models produced are used in synthesis, timing-driven place-and-route, static-timing analysis, power analysis, and functional verification. DynaCell's unique technology offers many benefits to the user such as ease of setup and execution, automatic function extraction, vector generation, optimum slope/load table selection, and timing and power characterizations in a single run. Built-in validation ensures high quality. DynaCell's automatic datasheet generation enhances usability and presents the user with a compact view of characterization results. CSI's built-in SPICE engine increases throughput without loss of accuracy.

DynaCore - A timing sign-off solution for custom block and full chip static-timing analysis for SoC, with SPICE accuracy and built-in optimum vector generation.
DynaCore is a next-generation, timing analysis, and modeling tool for multi-million-transistor designs. Designers have the capability to time the entire design at the SPICE level, using either Circuit Semantics' built-in SPICE engine or an external commercial simulator, and then running Circuit Semantics' STA. The DynaCore STA environment allows both custom and ASIC design flows to co-exist. DynaCore enables designers to quickly analyze timing bottlenecks, produce critical and sub-critical paths, slack analysis, and various types of timing models.

DynaModel/DynaTest - An automated Verilog Model generation of custom designs for functional validation and ATPG with an interface to Mentor's FastScan
DynaModel extracts a Verilog gate-level simulation model from custom designs including hard IP. All logic in the initial transistor-level design is precisely represented in the resulting Verilog model. It handles both static and dynamic design styles. DynaModel significantly accelerates functional simulation. It models a transistor-level design at a higher level of abstraction for use in verification flows signoff.

Benefits to End User of Product and Interface to MGC

Circuit Semantics' characterization, model generation and static timing solutions shrink time-to-market and reduce development costs.

CSI's software generates complete, reliable timing, power and functional models, accurately measures path delays to within 2% of SPICE and characterizes the most complex cell libraries.

The master database and unique core technology provides the power to enable the fastest execution speeds.

The only incremental characterization solution for maximum throughput and peak engineering productivity.

Company Background
Founded in 1997, Circuit Semantics is a team of highly skilled engineers, inventors, and management professionals. Circuit Semantics has developed products that simplify the tasks of designing high performance IC's using advanced design styles and complex logic techniques. These products handle mixed-level designs which encompass transistors, gates, blocks, and systems-on-a-chip. Circuit Semantics products work well with custom, structured custom, and ASIC methodologies. Our approach brings ASIC-like productivity levels to custom design, and the performance and accuracy of custom designs to ASICs.

Description of Integration
For high-performance design, DynaCell can be invaluable in the characterization of cell libraries, where the strategy is to use special cells, such as complex logic with many inputs, domino logic, or, differential logic, with ASIC methodology. For structured-custom methodologies, DynaCore and DynaModel can handle leading-edge design styles to perform block and chip-level timing analysis, with custom-block functional modeling. Special functionality has been developed in DynaModel and its companion module DynaTest to speed up the development of a comprehensive ATPG solution with FastScan from Mentor. All of the Circuit Semantics solutions enhance and broaden Mentor's IC and ASIC design solutions.

 

Platforms Supported

Distribution and Contact Information