SynaptiCAD Inc.

TestBencher Pro, Wave Former Pro, DataSheet Pro

Supports VHDL and Verilog simulation tools and timing analysis tools

Product Description
SynaptiCAD offers a complete line of HDL and timing visualization tools including: TestBencher Pro - test generation, WaveFormer Pro - waveform translator, VeriLogger Pro - Verilog simulator, DataSheet Pro - documentation tool, and Timing Diagrammer Pro - timing diagram editor. The following are descriptions of just some of the SynaptiCAD's products which complement the Mentor Graphics board level design and HDL level design products.

TestBencher Pro generates reactive VHDL and Verilog test benches and bus-functional models from language independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. An excellent tool for testing large FPGA and ASIC designs.

WaveFormer Pro combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator to form a groundbreaking EDA tool that should be in every digital designer's tool kit. WaveFormer Pro allows you to automatically generate and simulate timing diagrams using common Boolean and registered logic equations. WaveFormer Pro can also import or export waveforms to VHDL, Verilog, Tektronix & HP's logic analyzers & pattern generators, SPICE, ABEL, and a variety of gate level simulators including Mentor's QuickSim II.

DataSheet Pro provides documentation professionals with a more efficient environment for the management of documents containing multiple timing diagrams. The product uses Object Linking and Embedding (OLE) to provide immediate in-place editing of timing diagrams. Other features include style sheets, view support, direct web file generation, project management, and support for the industry-standard Timing Diagram Markup Language (TDML) format. Documentation professionals will be able to receive timing diagrams produced by design engineers using any TDML-compatible product, such as WaveFormer Pro or Timing Diagrammer Pro, and embed them directly into documentation programs like FrameMaker and Word.

• ModelSim and Renoir users can drastically reduce test bench coding and verification time by automatically generating self-checking, VHDL and Verilog test benches with TestBencher Pro's graphically entered, reusable timing diagrams.
• Exampler and ICX Synthesis users can describe their timing constraints using WaveFormer Pro's timing diagram editors.
• Save days of verification time, by using WaveFormer to translate VHDL and Verilog ModelSim test benches into Tektronix and Agilent Pattern Generator Stimulus files. And in the opposite direction, use WaveFormer to translate Agilent and Tektronix logic analyzer data into VHDL and Verilog models.

Company Background
SynaptiCAD is the industry leader in timing diagram editing and timing analysis products. Founded in 1992, SynaptiCAD has developed several products including an interactive verilog simulator, a VHDL and Verilog test bench generator, and a waveform translator that incorporates the timing diagram editing and timing analysis features.

Description of Integration
TestBencher Pro produces test benches that can be used with Mentor's Renoir / ModelSim / FPGA Synthesis suite of tools. TestBencher Pro also can launch the ModelSim simulator and feed both the generated test bench and the model under test to ModelSim to perform the simulation.

WaveFormer Pro provides both a front-end interface for creating models for Tau and a post-analysis environment for exploring design choices based on the results of the analysis. Minor modifications to WaveFormer would enable it to also generate synthesis constraints for FPGA Synthesis and possibly ICX as well. WaveFormer also provides Mentor users with links to the majority of logic analyzers and pattern generators.

Platforms Supported

Distribution and Contact Information