Design-For-Test (DFT)
- Methodology to ensure a design works correctly after manufacturing
- DFT tools add test circuitry (RTL or gate level) for design testability
- DFT tools generate test sets applied to manufactured designs to detect defects
- DFT-based diagnostics facilitate failure analysis
DVCon Keynote by Wally Rhines
In his keynote address, Wally Rhines talks about scan, ATPG, BIST, test pattern ordering, cost of test, Janusz Rajski, don't cares, coverage, at speed, stuck at, compression, transition and bridging faults, cycles-per-test vs. tests-per-cycle, 70% of design is test, and his Q&A follow-up.
Technical Events:
- EDA Tech Forum (New Delhi) Aug 20, 2008 - New Delhi, IN
- EDA Tech Forum (Bangalore) Aug 22, 2008 - Bangalore, IN
- EDA Tech Forum Sep 5, 2008 - Tokyo, JP
News and Related Articles
- Mentor Graphics Outlines IC Implementation Strategy to Address Sub-45nm ChallengesJun 9, 2008
- Mentor Graphics Aligns Product Groups to Address IC Implementation Challenges at 45nm and BeyondMay 7, 2008
- Mentor Graphics Announces Partnership with NXP Semiconductors for Design-for-Test Tools and TechnologyMay 6, 2008