Design-For-Test (DFT)

NEW: TestKompress Xpress

  • Methodology to ensure a design works correctly after manufacturing
  • DFT tools add test circuitry (RTL or gate level) for design testability
  • DFT tools generate test sets applied to manufactured designs to detect defects
  • DFT-based diagnostics facilitate failure analysis

Featured Design-For-Test Techpubs

Embedded Deterministic Test - DFT Technology for High-Quality Low-Cost IC Manufacturing Test

As the semiconductor technology migrates to 0.13 micron and below, it is becoming increasingly clear that test sets for single stuck-at faults alone are not sufficient to achieve the required quality levels. At 0.13 micron and below, circuits are more susceptible to speed related defects and hence to attain good quality, at-speed test sets such as those based on transition and path delay faults are necessary. While these additional test sets improve the test and product quality, they further exacerbate the problem of rising test data volume and test application time.

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Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test

The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Reduced pin count testing (RPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying RPCT, devices can be easily tested on structural DFT testers at a cost of about $200/pin compared to the high-end functional testers that cost almost $8,000-10,000/pin.

By combining RPCT with test compression, we have extended the capabilities of multi-site testing to allow application of at-speed test patterns using low-cost testers that are seriously pin-limited. We were able to free up device I/O by 90%. The method proposed here enables gains in test coverage with less application time and minimal effects on design and test overhead. It can be used in multi-site test, with simpler fixturing.

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High Quality Test Solutions for Secure Applications

Designs for secure applications such as smart cards and those used in the defense industry require security to ensure sensitive data is inaccessible to outside agents. Conversely, scan chains have been used for decades to improve access to internal logic for automatic tester equipment (ATE) so that devices can be tested efficiently and quickly. This conflict in requirements has forced many designers of secure applications to use logic BIST and sacrifice test quality in some cases, or perform deterministic scan test in very costly secure test environments. Contributing to these challenges are the ever-increasing requirements for high quality test and additional test requirements for fabrication processes at smaller geometries. In this paper, we will explore the techniques currently in use for testing devices designed for secure application and review the benefits and challenges of each available solution.

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