IC Nanometer Design

  • Efficient handoff between IC design and manufacturing
  • Provides necessary tie between physical verification and DFT
  • Single, streamlined design flow for AMS SoC design

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Featured IC Nanometer Design Techpubs

Reducing IC Cycle Time with Calibre

Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physical verification should take longer and why we should be given more time than we had for our previous project. As nice as that would be, this is not the case. Increasing competitive environments and the always present compulsion to get products out to market in a timely manner have not permitted such luxuries. Fortunately, despite conspiring forces to elongate this already difficult task, there is a light at the end of the tunnel (no, not a train coming the other direction), the Calibre suite of verification tools, specifically Calibre nmDRC, Calibre nmLVS and Calibre Incremental DRC.

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Setting MRC Rules: Balancing Inspection Capabilities, Defect Sensitivity and OPC

One of the challenges associated with shrinking design dimensions is finding photomask inspection settings which achieve sufficient defect detection capabilities while supporting aggressive Optical Proximity Correction (OPC). The most recent technology nodes require very aggressive and advanced Resolution Enhancement Techniques (RETs) which involve printing small features that are challenging for mask inspection tools. We examine the problems associated with constraining Models-Based OPC with mask inspection driven rules. We give examples of a 45nm technology node contact layer design which will receive sub-optimal OPC treatment due to mask inspection constraints. We then take the mask defect specification typically used for this mask layer, and use Monte Carlo simulation methods to place minimum sized simulated defects in various locations in close proximity to these sensitive layouts.

Simulations of the optimal OPC are compared to optimal OPC with defects, and to the sub-optimal constrained OPC. Using knowledge about the frequency of small defects on masks, one can compare the risks associated with small mask defects to the risks associated with sub-optimal OPC. This exercise demonstrates that there are some instances where mask rules based on inspection capabilities and defect sensitivity alone can be problematic, and that OPC requirements need to be taken into account when choosing a defect specification and an inspection strategy. We conclude by proposing a strategy for balancing these requirements in a practical manner.

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Featured Products

Olympus-SoC

Next-generation place and route system that concurrently addresses variations in lithography, process corners and design modes.

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Pinnacle

The industry's first IC implementation solution that comprehensively addresses the performance, capacity, time-to-market, and variability challenges occurring at the 65nm and 45nm process nodes.

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Calibre nmOPC

Next Generation High Performance RET Technology.

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Calibre nmDRC

New Hyperscaling processing architecture produces best-in-class DRC run times with scalability to 100 CPUs.

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