USB 3.0 is rapidly being adopted by a growing number of system level companies, spawning many integrated device manufacturers (IDMs) to develop new chips to address this need. USB 3.0 supports data transfer rates up to 4.2 Gbits/sec, creating new challenges for IC package designers and signal integrity engineers that must be addressed as part of the high-speed SERDES design process. These higher data rates will require substantially improved modeling accuracy of the IC package’s interconnect, wire bonds, vias, and solder balls that are part of such high-speed data paths. Now, full 3D electromagnetic (EM) simulation and modeling is required for such structures to help ensure the package design is optimized for low crosstalk (EM coupling), reflection, and insertion loss. This paper will introduce important design considerations and an effective high-speed design methodology recently successfully employed for the design of a commercial USB 3.0 part.