46th DAC / Hitachi reports 8 tape-outs with Catapult C
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Posted Jul 30, 2009
by Thomas Bollaert
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Looking at my San Francisco schedule, Tuesday was clearly the day I was most looking forward to. Besides the usual panels and meetings, I was really eager to hear the two testimonials from Hitachi Telecom and STMicroelectronics on their experiences with C Synthesis. Both Natori-san and Nitin Chawla provided personal and insightful views on their adoption of HLS
- 82% time reduction with C synthesis
Hitachi Telecom opened the discussion at 9am in the morning. There were so many registrations for Natori-san’s presentation that his session had to be moved to a larger room. Natori-san was not short on details regarding his latest developments with Catapult C. In the past 3 years Hitachi completed 8 tape-outs with the tool, the most recent being an 11.4mm² ASIC implementing enhanced forward error correction (FEC) algorithms for Hitachi’s broadcasting systems. Using Catapult C, Natori-san and his colleagues have been able to implement 57% of the entire ASIC in 82% less time than if manually coded.
Hitachi's FEC and Enhanced FEC ASIC
- Doubts and Convictions
That’s a lot of impressive numbers which truly reveal the benefits of C synthesis. But in my opinion, the most interesting was Hitachi’s description of the fears and doubts they had to overcome prior to engaging with Catapult C.
A methodology change is always source of anxiety. Balancing the risk/reward factor is not an easy task, the status quo being such a comfortable decision. I have to give credit to Natori-san for openly exposing all their hesitations, and how they surmounted them. The biggest hurdle to succesful adoption of C synthesis is not a technical one, it is a psychological one. I hope Natori-san’s example will inspire others.
Preparing RecommendationsBeing able to synthesize from pure C++, a language familiar to all and widely used by the algorithm team, made it much simpler to begin with. This was a key decision factor for Hitachi when selecting their HLS tool. And when the initial benchmarks showed results equal or better than hand-coded, Natori-san and his colleagues knew they had made the right choice…
Later in the day, STmicroelectronics would confirm Hitachi’s findings in a captivating testimonial on designing complex systems using C synthesis.
About Thomas Bollaert
My first encounter with HLS, back then behavioural synthesis, dates more than 15 years. Since then my ventures have led me to explore many aspects of the ESL design flow, including HW/SW co-design, architecture exploration and of course, C synthesis. Five years ago, I joined Mentor to develop the Catapult C product line in Europe. Recently, my little family followed me all the way from Paris to Oregon, where I now serve as product marketing manager for Mentor Graphics' high-level synthesis product line.
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4 Comments on this Post
Commented on 7:34 AM, Jul 30, 2009
By 46th DAC / STMicroelectronics designs a Frequency Domain Processor out of pure C++ « Thomas Bollaert’s Blog
Commented on 6:16 AM, Aug 5, 2009
By Sean Murphy
Commented on 1:56 AM, Aug 6, 2009
By Thomas Bollaert
Commented on 3:19 AM, Oct 21, 2009
By wallmart
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