Emulation 104 -- Running More Tests in Less Time

In an earlier blog I talked about the value of emulation in terms of providing direct project cost and schedule reductions that generally dwarf the actual costs of emulation systems. I have been asked by some to provide a “prequel” discussion, with a higher level description of the SoC verification problem and how emulation systems address verification challenges.

Rather than trying to cover the universe of SoC verification problems all at once, let me address a few of those challenges in a couple of blog posts. You will see that emulation systems can address most the challenges in one way or another — by themselves, by complementing other tools, or replacing other equipment and verification tools altogether.

So let’s start with a look at what is going on to generate better, more complete functional verification tests, and then how emulation executes them in less time.

As designs have become more complex, new test methodologies and test generation tools have evolved to complement traditional manual, directed testing. These principally include constrained random tests and tests generated by high level, behavioral test benches. While easier to create, the resulting test suites tend to be extremely large, and long simulation runtimes just get longer, exacerbating the verification schedule problem.

Emulation systems are a perfect complement to these test development tools. When run as simulation accelerators, emulation systems deliver throughputs hundreds or thousands of times those of simulators. Weeks of tests are reduced to hours, and days of tests to minutes.

Further, verification methodology has evolved with new standards. For example, OVM provides transaction-based verification with interoperability between standards compliant simulation and emulation environments, making testbenches re-usable. Many high-level testbench constructs can now be synthesized for use in emulation by tools like Mentor’s System Verilog extended RTL compiler (xRTL compiler). This enables timed portions of the testbench to be executed within emulation system hardware with the DUT and talk through Acellera and Verilog standards-based communications to untimed portions executing on a host. The result is that both the DUT and testbench are accelerated.

Consequently, emulation enables running larger, more complex testbenches several orders of magnitude faster than simulation, resulting in much shorter verification time and generally a portion of the verification time savings passing directly to project schedule shortening the time-to-tapeout of the SoC. Further, testbench interoperability between simulation and emulation maximizes the productivity of adopting the latest test bench generation tools and verification methodologies.

As always, comments are welcome. For more information on Mentor’s Emulation Systems go to www.mentor.com/products/FV/emulation-systems/

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