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More uses for an MMU

Some time ago, I wrote about the use of a memory management unit (MMU) for embedded applications and covered the basics of what such a device can do. Recent comment on that posting inspired me to think more about how an MMU may be used more creatively.

The basic function of an MMU is to control a relationship between the addresses that a CPU uses to access specific memory areas and their actual physical address. It can also deny access to specific memory areas entirely. This functionality is controlled by information written to a number of registers in the device. These registers are normally accessed by the operating system so that the view of memory changes, depending on which task is currently running. This is the conventional application of an MMU and is useful, but there are other possibilities …

An MMU is normally associated with process model operating systems [like Linux and Windows, for example]. As each process is scheduled, its area of physical memory is mapped into the logical space beginning at zero. Thus, each task [along with the operating system itself] is protected from unauthorized access by other processes. A thread based operating system – like most embedded OSes – may still use an MMU, but, instead of remapping addresses, it simply uses the device to protect memory areas. I discussed this in a previous blog. It is an option with Nucleus.

There are more creative ways to use an MMU. I wrote about one possibility [which is probably not viable] to manage a heap and avoid fragmentation. I need to think about that some more, but some other ideas have been proposed:

Any subsystem that uses memory buffers could use an MMU to protect them, making them visible only when access is authorized. This might apply to file systems, networking interfaces, inter-CPU communications etc. This is quite a “light weight” application of an MMU [like Thread Protected Mode] and would not impose a significant overhead. The buffers would be protected from malfunctioning or malicious code. Any malware would also need to access the MMU, which, though not impossible, makes life much more difficult for the hacker.

The entire memory of a device could be remapped in a somewhat random fashion. When the device starts up, it would await the instruction and information to unscramble the memory map from a trusted external source. This instruction could be protected using standard [public/private key?] encryption. Using this approach, a device could be stolen and taken apart by someone with criminal intent, but they would have no way to figure out the meaning of the memory contents. Of course, similar results could be obtained using memory encryption, but this requires additional, specialized hardware and introduces further challenges [like debugging].

I would be very interested to hear about other imaginative ways in which an MMU may be employed by email or comment.

[Thanks to Charles, whose comment made me think about revisiting this topic.]

Linux, memory management unit, RTOS, MMU, Nucleus

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About Colin Walls Follow on Twitter

Colin WallsI have over twenty-five years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles and two books on embedded software, I am a member of the marketing team of the Mentor Graphics Embedded Systems Division, and am based in the UK. Away from work, I have a wide range of interests including photography and trying to point my two daughters in the right direction in life. Learn more about Colin, including his go-to karaoke song and the best parts of being British: http://go.mentor.com/3_acv Visit The Colin Walls Blog

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In addition to remapping logical-to-physical addresses, and controlling access, many MMUs also control caching behavior and write-through/copyback behavior in devices with a write buffer. The Freescale MPC8xx (and 8xxx, and all their brethren, uncles, and third-cousins twice removed) are examples of this. Back in the late 90s, I came in to rescue many MPC8xx designs, and often the engineering team would say "We're not using virtual memory, we don't need to use the MMU." Assuming you want high-performance and proper operation, you can't avoid using the MMU on these chips. It's been a little while since I worked on an ARM w/ an MMU, but I believe there are similar attributes. Maybe MIPS too, I can't recall. (x86 - don't like the thing, don't know anything about it!)

Dan
7:32 PM Dec 6, 2010

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