The Devil Inside

In a recent blog post, Harry Foster looks at the growing the challenge of design debug. Numbers generally vary when it comes measuring the actual impact of debugging in the project cycle, but they also have one thing in common: they are significant. The post points to two surveys showing that amount of time spent debugging jumped from 42% of the verification cyle in 2003 to 52% in 2007. If verification is the bottleneck of ASIC design flow, then debug is the bottleneck in the bottleneck.

So what do we do to address the issue? Harry suggests that there is no silver bullet for this and advocates for a “multifaced solution“.

But what if instead of trying to simply the debugging the challenge, we aimed to eliminate it?

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If verification and debug has grown to be such a problem these days, it is because of our inability to design correctly to start with. While verification methodologies have greatly evolved with SystemVerilog and OVM, designs are still created with flows, languages and abstractions originally deployed in the early 90’s. RTL design flows are running out of steam, but preserving the status quo in hardware design puts the burden on the verification teams.

If we ambitioned to create bug-free designs, generating them in a correct-by-construction fashion from high-level specifications, the verification task would obviously be made a lot easier. Confirming this trend, 68% of respondents to a recent industry survey ranked “reducing the verification effort” their #1 motivation for adopting high-level synthesis (HLS).

For sure “error is human”, but is this a reason to accept bugs in our designs?

                                        errare humanum est, sed perseverare diabolicum

 And if this topic is of interest, you might be interested in this article: Boosting RTL Verification with High-Level Synthesis

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