A Comprehensive Solution for SoC Development for Embedded Systems
Join us for this four part seminar will cover the following topics
Part 1: “C to FPGA”: Mapping Algorithm to FPGA using Vivado High Level Synthesis Tool.
Is the high level synthesis tool ready for prime time? How is the quality of results (QOR)? How difficult is it to achieve QOR using such a tool? How does it compare to conventional RTL design entry? The Xilinx folks will introduce Vivado High Level Synthesis tool, which synthesizes the C/C++/SystemC code into synthesizable RTL; and try to address those key questions.
This session is presented by Alex Paek
Part 2: Your custom SoC needs its own carefully tuned instruction set architecture designed to make maximum use of every transistor to deliver the performance your application needs.
This is true for a DSP, a VLIW network processor, a massively multicore image processor, or a superscalar deeply pipelined predicated execution SIMD engine with special-purpose statistical counters. You can program your SoC in assembly language. And, for inner loops and critical code paths, you certainly will. But, there's a lot of control code needed. You might even want to run Linux or uClinux, or at least an RTOS. Your application programmers aren't all going to find it easy to become experts in a special-purpose assembly language and will need to program in C or C++. There are two strong open-source technologies that you could use to build a C/C++ compiler (and related tools) for your SoC. You can use the GNU toolchain, including GCC, GDB etc. the venerable market leader, used to build Linux, Android™, and real-time operating systems like Nucleus®. Or, you can build a LLVM toolchain, a newer toolset used by Apple® to build OS X® and iOS®.
- This session is presented by Mark Mitchell
Part 3: Overview of SiLabs' EFM32 micro controller family.
We will discuss the 10 factors that make EFM32 the world's most energy friendly MCUs, key applications, SW tools, and success stories.
- This session is presented by Raman Sharma
Part 4: The Xilinx All Programmable SoC, Zynq-7000 represents a relatively new alternative in the embedded landscape.
It does not face the same challenges as traditional processors, ASSPs, and SoC’s because this innovative device is designed to be leveraged across multiple markets in multiple products while permitting customization through software, hardware, interconnect, and I/O. The Zynq All Programmable SoC has a unique architecture that combines dual ARM Cortex A9 processor cores with programmable logic and programmable I/O that takes advantage of familiar, SoC-like design tools and methodologies. The Vivado Design Suite provides multiple design entry points in C, C++, HDL, System C, MatLab, and LabView that allow system architects and designers to enter the design flow at a familiar level.
- This session is presented by Larry Gettman
What You Will Learn
- Overview of Vivado HLS
- Library suppor, floating point library, OpenCV
- C-synthesis and optimization process
- Design examples – matrix operations, video application
- The differences between the GNU and LLVM toolchains
- The steps necessary to build a C/C++ compiler for a custom instruction set architecture
- The challenges of building a C/C++ compiler
- The licensing implications of using open-source software with a highly proprietary SoC
- SiLab's new EFM32 portfolio.
- 10 factors that make EFM32 the world's most energy friendly MCUs.
- How to optimize energy efficiency using Simplicity Studio.
- The current landscape for embedded design alternatives: embedded processors, ASSPs, SoCs, and All Programmable SoCs
- The types of systems that particularly benefit from the combined processing and I/O capabilities of Zynq All Programmable SoCs
- How the Xilinx Zynq-7000 All Programmable SoC and the Vivado Design Suite permit the rapid and efficient development of sophisticated, single-chip hardware/software systems.
About the Presenters
Larry Gettman is in charge of marketing team and all marketing activities for Xilinx's Processing Platforms including the Cortex-A9 ARM SoC + FPGA Zynq-7000 family of products as well as the embedded SW tool chain (SDK), runtime and embedded tool partnerships and associated embedded IP.
Mark Mitchell is the General Manager of open source solutions for the Mentor Graphics Embedded Software Division. Before joining Mentor Graphics, Mark Mitchell was the founder and Chief Sourcerer of CodeSourcery, Inc., which Mentor acquired in 2010. Mark has worked on C/C++ software development tools since 1994, and has been involved in Free Software Foundation’s (FSF) GNU Compiler Collection (GCC). Since 2001, he has been an active member of the GCC Steering Committee. He holds degrees in computer science from Harvard University and Stanford University.
Raman Sharma is a technical business leader with 15 years of experience ranging from chip design to sales and marketing. At Silicon Labs, Raman is responsible for MCU and wireless marketing actives in the Americas. Prior to joining SiLabs, Raman was the VP of Sales Americas for Energy Micro where he helped to create a business for EFM32.
Who Should Attend
- Business owners responsible for software enablement of SoCs
- Designers of SoCs
- Compiler developers
- Embedded tools developers
- HW and SW engineers that care about low power designs and battery life for their portable or wearable products.
08:30 – 09:00 Registration
09:00 – 10:00 Xilinx HLS ("C" To Gates)
10:15 – 11:45 Mentor Embedded Tool Chain
11:45 – 13:00 Lunch
13:00 – 14:00 Silicon Labs
14:00 – 15:00 Xilinx Zynq SOC Futures