Electronic System Level Design
Achieving Optimal Designs though Electronic System Level (ESL) Methodologies
High Level Synthesis On-Demand Web Seminar
Learn how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms.
Today’s advanced designs have grown too massive and complex to cost-effectively design and verify using traditional RTL methodologies alone. This trend toward increasing complexity has led to more ASIC re-spins, lost revenue from missed design deadlines, and sub-optimal systems that are larger, slower or consume more power than required.
Electronic System Level (ESL) design methodologies address this complexity problem by elevating design to a higher level of abstraction. This relieves hardware designers from the design errors caused by the overwhelming detail of lower-level methodologies. Even more important, the single source methodology eliminates the most common source of errors between the system designer and the hardware designer. Designers can now use SystemC transaction-level modeling (TLM) to quickly perform architectural tradeoffs for power, performance and area, and evaluate hardware/software interactions. Designers can also use best-in-class high-level synthesis technology to support TLM-based processes, and automate the creation of optimized RTL implementations. Using this methodology, designers can create, optimize and verify designs that are tailored to their specifications 10-100X more efficiently than traditional methodologies.
Featured ESL Techpubs
Utilizing SystemC for Design and Verification
The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.
The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.
This exhaustive examination includes dozens of graphics, a glossary and code appendix.
Hardware/Software Validation with a TLM Virtual System Prototype
With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer products, allowing the system company to reap substantial profit margins. Software is also key in the power and performance behavior of the hardware platform.
Technical Events:
- 6th ESL Symposium Panel Discussion at DAC 2008
- online
- Efficient Model Creation for Transaction-Level Methodologies
- online
- High Level Synthesis On-Demand Web Seminar
- online
News and Related Articles
- Mentor Graphics and Altera Partner on DO-254Aug 19, 2008
- Mentor Graphics New Version of Platform Express Supports IP-XACT 1.4 Specification from The SPIRIT ConsortiumMar 18, 2008
- Mentor Graphics announces Catapult C Synthesis Accelerated Libraries for Xilinx High-Performance Virtex-5 FPGAsJan 22, 2008