A Complete TLM 2.0-based Solution
Today’s advanced designs have become too massive and complex for traditional RTL methodologies. Electronic System Level (ESL) design methodologies address this problem by elevating design and verification to a higher level of abstraction, where many engineering tasks and design optimizations can be successfully accomplished more quickly, more efficiently, and more cheaply than at the RTL.
Vista™ is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping. Vista enables system architects and SoC designers to make viable architecture decisions, and it allows hardware and software engineers to validate their hardware and software early in the design cycle.
This is accomplished by prototyping, debugging, and analyzing complex systems before the RTL stage, establishing a predictable and productive design process that leads to first-pass success.
Vista Use Models
Architecture design is carried out by system architects and SoC designers, who architect the system topology. They use an iterative exploration process by simulating, analyzing and optimizing the architecture to meet power and performance objectives. Architecture Design Exploration
Architecture validation focuses on verifying and debugging at the transaction level. System designers and verification engineers need to simulate and validate that the system functionality and the interaction among design blocks is correct, and they need to debug any errors found at the system level. Architecture Validation
The Vista flow consists of the steps typically used by SoC architects, hardware engineers, and software engineers to create transaction-level models, assemble and configure the system, simulate, verify and debug the system, analyze and optimize performance and power and integrate hardware with software.
Transaction-level modeling (TLM) is one a key ESL methodology that allows transaction-level model creation. It includes modeling the functionality, the timing, power, and communication interfaces at a higher level of abstraction. Transaction Level Modeling (TLM)
ESL Design, Verification & Virtual Prototyping
System developers face significant challenges to integrate complex hardware with software running on multi-core processors and to comprehend the combined impact of the architecture on system power, performance, and functionality. The most common approach used in the past was to develop the system hardware and software components in isolation, waiting to integrate and test their interactions at the end of the design cycle. As a result, product development time was longer and the opportunity to make architectural modifications was lost.
Creating transaction-level platforms early in the design cycle ensures that the system can implement the desired functionality while handling its load and data traffic capacities. Furthermore, it allows for validating the software against the hardware even before RTL is implemented and tuning the multi-core hardware architecture and embedded software to meet performance and low power requirements.
Key Questions (at the architecture level)
- Can the architecture deliver the necessary functionality and meet user expectations?
- Can the system meet performance and power consumption goals?
- Can the system specification be effectively implemented?
- Can software run correctly and efficiently on the target architecture?
Before and After: Optimizing Performance