ESL design methodologies allow engineers to perform design optimizations on today's advanced designs more quickly, efficiently and cost-effectively than with traditional RTL methodologies, by prototyping, debugging and analyzing complex systems before the RTL stage.
ESL establishes a predictable, productive design process that leads to first-pass success when designs have become too massive and complex for success at the RTL stage.
Vista Use Models
Vista Use Models
Vista™ is an integrated TLM 2.0 solution for architectural design exploration, verification, and virtual prototyping. It enables viable architecture decisions and hardware and software validation, early in the design cycle.
ESL Design, Verification & Virtual Prototyping
Creating transaction-level platforms early in the design cycle ensures that complex hardware systems can handle required functionality at full load and data traffic capacities. It also allows engineers to validate software against hardware even before RTL is implemented, including testing software running on multi-core processors, and comprehending the combined impact of architecture on system power, performance, and functionality.
Today, ESL design, verification and virtual prototyping eliminate the need to develop system hardware and software components in isolation, to be integrated and tested only at the end of the design cycle. As a result, product development times can be greatly shortened, and the opportunity to make architectural modifications with relatively low impact has been extended.
This enhances designers' ability to tune multi-core hardware architectures and embedded software to meet the most stringent performance and low power requirements.
Before and After: Optimizing Performance
Key Questions (at the architecture level)
- Can the architecture deliver the necessary functionality and meet user expectations?
- Can the system meet performance and power consumption goals?
- Can the system specification be effectively implemented?
- Can software run correctly and efficiently on the target architecture?