46th DAC / San Francisco’s other Marathon

It is early Sunday morning in San Francisco. I am tranquilly having breakfast in a nice little coffee place when a cheerful crowd draped in silvery blankets enters the bar. It takes me a few minutes to figure out that I am facing a group of people who just finished the San Francisco Marathon! 

I have to admire the determination it takes to prepare, run and complete such a race. Meanwhile, the Moscone center is buzzing with booth builders setting the stage for the week ahead, and I can’t help thinking that San Francisco is about to host a second, yet very different, marathon.

• MSE Conference

My own little marathon started the day before, on Saturday. I was invited at the MSE conference to give a 3:30hrs tutorial on Catapult C. The turnout was really good and above expectation. But most importantly, the quality of the questions and interactions really demonstrated acute knowledge on the topic. The evolution in people’s understanding of high-level synthesis, of how it works and what it can do, is striking. In my opinion, this is a faithful representation of the traction the technology is getting in the industry.

• Multi-block hierarchical synthesis from pure C++

On Sunday, I had the opportunity to meet with several Catapult C customers, reviewing their recent achievements with the tool. One of them recently completed a very big hierarchical design containing 7 sub-blocks. The project manager was still marveling at what had been accomplished. He openly admitted his initial skepticism at the idea of building multi-block hierarchical systems from sequential C++ - but seeing is believing and Catapult really exceed his expectations. Now the next thing they want to try is Catapult’s new multi-level clock-gating optimization for low-power.  

• Vista Architect – managing power ahead of implementation

Preparing Recommendations

Monday morning, 8:30am. Mentor Graphics holds a press conference to announce its new Vista product line for low-power design and optimization at the system-level. This is really new and exciting technology. System-level is where you can have the biggest impact on power consumption. This is where the overall architecture is defined and optimized; this is where the SW partition is balanced and tuned… by doing things correctly upfront, the opportunities to save power are significant. And that’s exactly what Vista helps designers with. To make things even better, Catapult C integrates with Vista to automate the generation of transaction-level models (TLM) for power analysis. The result is a combined flow to design and optimize power across design scopes: from the system-level all the way to implementation, through synthesis.

• “Standing Room Only”

Monday morning, 11am. I am giving a Catapult presentation in the Mentor suites. The topic: a detailed talk on our new technology for control-logic synthesis and low-power optimizations. Wow! The room is packed, there are twice as many people showing up as we can sit in the room. Later on in the afternoon, my colleague Bryan Bowyer hosts another session, and once again it’s standing room only. I guess John Cooley was right: Catapult C is the “#1 must see” product at DAC this year!

Tuesday, designers from Hitachi Telecomm (9am) and STMicroelectronics (4pm) will present their results using Catapult C in the Mentor suites. If you are interested in C synthesis, I highly recommend these sessions. But come in early, or might have to stand in the back!

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Preparing Recommendations