48th DAC - Gary’s Magic Formula

Last night, in his traditional DAC-opening presentation, Gary Smith addressed the crowd with a loud and clear message about the cost of doing hardware design. Design costs are steadily increasing and this is draining life and blood out of the industry. When chip design costs reach $25M, VCs stop funding start-ups. When costs reach $50M, continued Gary Smith, even IDMs struggle to afford ASIC developments.

So where do we stand today? According to Smith, too many projects require 100+ hardware engineers to complete a chip, putting design costs way too high to be affordable. Yet today, it is possible to design a 104 million gates ASIC with 30 engineers for the cost of $18.7M. Notice the present tense in the previous sentence: it “is” possible to do this today. These numbers were not pulled out of thin air; these are actual figures from a design house surveyed by Gary.

How does one design a large ASIC for less than $20M? The secret is in reuse and in proper design organization. Assuming 80% of RTL reuse, this means that out of your 100 million gates ASIC, 20 million gates need to be designed. In other words, 5 blocks of 4 million gates each. That’s Gary’s “Magic Formula” and the secret to cost effective hardware design.

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The corollary of this formula is that the minimum capacity for an EDA tool is too be able to handle a 4 million gates block in an overnight run. This is the strict minimum and anything less than that is not viable.

The math works out, and when you spice the formula with ESL and High-Level Synthesis, you can build an even more compelling economic case for your next ASIC. That’s good news and that’s certainly why Gary sees the EDA market on a solid growth path and reaching $6.6B within a few years.

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