Catapult C and the 7 Samuraïs

You may have already encountered the expression “Full-Chip High-Level Synthesis” on this blog. I typically define it as the ability to model, verify and synthesize complete IP subsystems starting from C++/SystemC. This obviously encompasses core processing functionality, but also control-logic, memories, hierarchy, complex interfaces and interconnects. In other words, being able to do the “full” thing, really.

A few days ago, “one of the seven samuraïs” posted on John Cooley’s ESNUG the results of his evaluation of Catapult C. As you’ll see from the requirements to handle arbitration logic and point-to-point interfaces on top of algorithmic content, this pretty much means “Full-Chip HLS”. Here is how the report starts:

• “We wanted our test to be rigorous, so we used an existing scaler design. Our scaler was implemented in 90 nm technology.  It does down and up scaling of frames from 1×1 to 1024×1024 pixels; each pixel has four 8-bit components.  The scale factors are configurable, with an integrated 640 pixel line buffer.”

The rest of it, including results found and conclusions can be read on here.

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