Catapult C users speak out at DAC

DAC is undoubtedly the best opportunity for EDA users to meet with their peers and share experiences about new and innovative design practices.

If you are looking for first hand feedback on Catapult C, don’t miss the two user testimonials in the Mentor Graphics suites. This year, presenters from Hitachi and STMicroelectronics will talk about their achievements with the tool and the deployment of a HLS based design flow in their organization.

Hitachi Telecomm has been using Catapult C Synthesis since 2005. Katsunobu Natori will present on their experience designing FEC (Forward Error Correction) in LSI (ASIC and FPGA) for Gigabit Ethernet Optical Network, in which they achieved 5X productivity improvement and area reduction to 1/3 using Catapult C Synthesis. Hitachi will also discuss how Catapult C has been introduced into their design environment.

  • This presentation will be held Tuesday, July 28th at 9am in the Mentor suites (#3567)

Nitin Chawla of STMicroelectronics will present the use of High Level Synthesis in an ESL design methodology for design of high performance signal processing hardware accelerators. Design space exploration at the algorithmic and architectural level is elaborated using model based design and C++ based high level synthesis. High level synthesis and its interaction with other design flow steps is highlighted to create an end-to-end ESL framework for ASIC design targets.

  • This presentation will be held Tuesday, July 28th at 4pm in the Mentor suites (#3567)

These user sessions are very popular and registration is highly recommended:

Preparing Recommendations

Lastly, my colleague Bryan Bowyer and I will be hosting two Catapult sessions every day, elaborating on the latest Catapult control-logic announcement and Mentor Graphics’ decisive innovations for low-power and full-chip synthesis. 

  • This presentation will run Monday through Wednesday at 11am and 3pm

 If like Gary Smith, you put C synthesis on top of your what-to-see list, and if like John Cooley you sense a tremor in the Force, be sure to stop by!

About Thomas Bollaert

imageMy first encounter with HLS, back then behavioural synthesis, dates more than 15 years. Since then my ventures have led me to explore many aspects of the ESL design flow, including HW/SW co-design, architecture exploration and of course, C synthesis. Five years ago, I joined Mentor to develop the Catapult C product line in Europe. Recently, my little family followed me all the way from Paris to Oregon, where I now serve as product marketing manager for Mentor Graphics' high-level synthesis product line. Visit Thomas Bollaert’s Blog

More Posts by Thomas Bollaert

More Blog Posts

Preparing Recommendations

Comments

No one has commented yet on this post. Be the first to comment below.

Add Your Comment

Please complete the following information to comment or sign in.

(Your email will not be published)