Defining Control-Logic

The design world is commonly separated in two camps: algorithmic-oriented designs and control-dominated designs.  By becoming the first High-Level Synthesis tool to synthesize Control-Logic from pure C/C++, Catapult C makes the promise that these two camps can be united enabling full systems to be modeled, verified and synthesized all together.

But this cleanly divided view of the world is only a convenient simplification of the reality. RTL engineers know better: control and algorithms are often tightly intertwined. This demands clarifications. What exactly is control-logic? How do we define it? Does every FSM in an RTL design fall in the “control-logic” camp in the context of HLS? Would you need to use the new Catapult C control-logic capabilities for each state-machine in your design?

Let’s take a step back and try to differentiate the various kinds of “control” commonly found in RTL designs and where the new Catapult C modeling and synthesis feature apply.

1. Algorithmic blocks can have plenty control and state machines. For instance, in a computational block, you’ll most likely have an FSM ramping up and down the pipeline as well as managing the time-sharing of expensive resources.

If this, without a doubt, qualifies as control, it is not the kind of control we are targeting with the new Catapult control synthesis announcement. As a matter of a fact, this kind of control has been natively supported in Catapult, right from its inception, more than 5 years ago.

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2. Inter-block communication also requires various forms of control. For instance, two video processing units might exchange data through double-buffered memories. This requires control to understand when blocks are running, when they need to switch buffers and when that switch can be granted.

But one of the beauties of synthesizing from pure untimed C++ is that this kind of control is implicitly described in the code sequence, eliminating the need for explicit and error-prone description in the source. It however takes intelligence from the synthesis tool to build the appropriate logic. And that’s precisely what Catapult C Synthesis can do through its hierarchical and channel synthesis capabilities introduced in 2006.

3. And then there are units where the primary function is control, not data processing. These implement things like arbitration schemes or cache policies. In this case, the control behavior is intimately tied to signal timing and has to be described in the C++ code by the user to be functionally complete.

The new Catapult C control synthesis enhancements have been created to model and verify just that: designs whose core functionality are control related and needs to be explicitly described. These are designs which typically have to act on every clock, regardless of data presence. Such blocks can be referred to as “synchronous reactive”. If you are designing an arbiter, a bus interface or a memory controller, the new Catapult 2009a release is made for you.

So what’s the take-away? There are multiple forms of control; and each of them is more efficiently expressed in a specific way. From today on, Catapult C lets you model, verify and synthesize any kind of control from its most appropriate representation.  That is the purpose of abstraction. And this is what springs the productivity advantage of Catapult C.

For more details, come see us in San Francisco, at the 46th DAC, on booth 3567. You can also register for a private suite presentation through Mentor Graphics’ website: http://www.mentor.com/events/design-automation-conference/

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