DVCon: All About Higher-Level

Well maybe it’s because I’m biased. Maybe because that’s how think. But at last week’s DVCon it really felt that it was all about high-level languages and higher-levels of abstraction to address the “D” and “V” challenges.

The titles in the tutorial and session programs were pretty explicit. SystemC and C++ were covered in most presentations, when it wasn’t SystemVerilog or better; a combination of all three like in one of Monday’s tutorials sponsored by ARM and Mentor Graphics and detailing a step-by-step guide to advanced verification.

Monday started with the 12^th edition of NASCUG - the North American SystemC User Group. Gary Smith kicked things early with his keynote and a valuable perspective on the ESL landscape following the recent shake-up in the virtual prototyping space and announcements in the high-level synthesis market. Brian Bailey has pretty good right-up on Techbites. Gary’s analysis is further detailed in the “Two Down Three to Go” research viewpoint he recently published:

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On Wednesday, Intel’s Zhu Zhou gave an interesting presentation on “Bridging the Gap between TLM-2.0 AT Models and RTL - Experiments and Opportunities“. While SystemC and TLM2.0 hold great promises, Zhou’s presentation pin-pointed the challenges in making them work in a real-life context. The crux of the problem is in the correlation between TLM2.0 and RTL models due to their different timing models. If the splitting of a TLM2.0 transaction isn’t without its problems, handling multiple completions to one original split transaction is even more challenging. The “plumbing” - consisting of transactors, checkers and monitors - required to make all this work can result in significant effort, and according to Zhou, high-level synthesis has a role to play to reduce it. Indeed, rather than investing time and effort to compare and verify two different models, it is a lot simpler to automate the generation of one from the other… an idea not foreign to the readers of this blog.

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