ESL Agenda
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Posted Feb 18, 2011
by Thomas Bollaert
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What is a Go URL?Oh my, what a busy ESL agenda! There is content for everyone, everywhere. Here is a list of no less than 7 compelling events. Virtual Prototyping, ESL Verification, High-Level Synthesis: make your choice. What’s on your agenda? Which events will you be attending?
- SystemC Day 2011 - February 28th, San Jose, CA
- High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application - DVCon, March 1st, San Jose, CA
- ESL Verification in the TSMC Reference Flow - Presentation - EDA Tech Forum, March 10th, Santa Clara, CA
- Practical Applications of High-level Synthesis - Presentation - EDA Tech Forum, March 10th, Santa Clara, CA
- Electronic System Level Design and Verification - Tutorial - DATE, March 14th, Grenoble, France
- Making ESL Design and Verification a Reality - Webinar Series - On-demand
- ESLsyn - Conference - June 5-6, San Diego, CA
About Thomas Bollaert
My first encounter with HLS, back then behavioural synthesis, dates more than 15 years. Since then my ventures have led me to explore many aspects of the ESL design flow, including HW/SW co-design, architecture exploration and of course, C synthesis. Five years ago, I joined Mentor to develop the Catapult C product line in Europe. Recently, my little family followed me all the way from Paris to Oregon, where I now serve as product marketing manager for Mentor Graphics' high-level synthesis product line.
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