Mentor ESL in TSMC Reference Flow 12

One year ago, I was writing about the inclusion of Mentor ESL in the TSMC Reference Flow 11, and why the endorsement of system-level design and high-level synthesis by the world’s leading foundry was a telling sign of maturity for ESL.

Since this first major milestone, TSMC and Mentor haven’t remained idle, on the contrary. Both parties teamed-up to take this first ESL flow to a whole new dimension, expanding the use of ESL and functional verification tools from single-block to full SoC design.

Today, this effort is released in the form of the new Mentor ESL flow in TSMC’s Reference Flow 12 targeting TSMC 28nm process technology. The Mentor ESL design and verification flow now addresses full SoC designs with support for transaction level model (TLM) based Virtual Platforms enabling early software validation, power estimation and model reuse and refinement to RTL:

• The Vista platform supports functional validation and power estimation based on TSMC iPPA process node value characterization, and enables OS booting and early validation of application software on a Virtual TLM Platform.
• Certe Testbench Studio provides automated Universal Verification Methodology (UVM) testbench creation, saving time and reducing errors.
• Catapult C supports high-level synthesis from SystemC and incremental synthesis, which is demonstrated on a complete, multi-block, hardware accelerator component. The generated RTL, including AXI interfaces, is combined with the Questa Verification IP and a TLM Virtual Platform running in Vista to provide a hybrid TLM and RTL simulation.
• Questa Ultra provides an ESL to RTL verification flow with UVM that supports TLM platform and model reuse, test plan tracking and accelerated coverage closure.
• Questa Codelink provides HW/SW co-verification to greatly reduce debug time when running system tests on an embedded processor.

If you are at DAC in San Diego, and if you are interested in seeing a full SoC TLM virtual prototype booting Linux, before synthesizing a complete IP subsystem from TLM to RTL and then verifying it with Questa Verification IP, then you may want to stop by the Mentor booth #1542 for a suite session and demo.