One of the best EDA releases of 2009

In a very thorough article published yesterday, Electronic Design’s David Maliniak takes a close look at ESL tools and how they are taking center stage as designers move up the abstraction ladder. The article reviews the details of the two major additions in the latest release of Catapult C: low-power optimizations and control-logic synthesis.

“Launched in 2004, Mentor Graphics’ Catapult C has seen continual improvement. Mentor has now fully endowed Catapult C with the ability to synthesize control-logic blocks, enabling it to synthesize full chips from ANSI C++ to RTL. It’s also one of the best EDA releases of 2009.”

The full paper can be read here.

Resonating with Dave Maliniak’s article, Tim Köppe of Nokia-Siemens-Networks (NSN) gave a presentation at the U2U conference in Munich on how he was able to implement a control-logic design doing memory handling for packet buffers using the latest capabilities of Catapult C. The full presentation is available the U2U website.

Nokia Siemens Network - A Networking Example with Catapult C

Nokia Siemens Network - A Networking Example with Catapult C

The presentation provides extensive details on how the desired high-throughput for this networking application could be met with a combination of code improvements and synthesis constraints.

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About Thomas Bollaert

imageMy first encounter with HLS, back then behavioural synthesis, dates more than 15 years. Since then my ventures have led me to explore many aspects of the ESL design flow, including HW/SW co-design, architecture exploration and of course, C synthesis. Five years ago, I joined Mentor to develop the Catapult C product line in Europe. Recently, my little family followed me all the way from Paris to Oregon, where I now serve as product marketing manager for Mentor Graphics' high-level synthesis product line. Visit Thomas Bollaert’s Blog

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