Ramping up with C Synthesis: practical learning resources

 Design complexity and design automation can be seen as the yin and yang of electronic engineering. They are interdependent and drive one another. Increasing design complexity mandates the adoption of new tools and methods, which in turn make designers more productive allowing them to create even more complex applications…

In the mid-90’s hardware designers adopted logic synthesis and moved up in abstraction, shifting from gate-level design to RTL. Today, new complexity thresholds are met and the design community is once again moving to more abstraction and increased automation using C synthesis.

But deploying new design techniques, while ultimately beneficial, doesn’t happen over night. From initial awareness to actual usage, there is a natural and necessary learning cycle. And since C synthesis is clearly entering the mainstream of hardware design, practical learning resources are more important than ever to help RTL designers through this ramp up phase.

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Today I’d like to highlight several resources which provide just this: the opportunity to learn about C synthesis from detailed and technical “how-to” sessions.

• EDA Tech Forum - Mobile Chip Design using High Level Synthesis

Three upcoming Tech Forums in Santa Clara (Sept 3^rd), Denver (Oct 1^st) and Boston (Oct 8^th) will discuss “Mobile Chip Design using High Level Synthesis”. Hardware for mobile devices has some of the most intricate design constraints of any ASIC development flow. Hidden away in most of the mobile devices manufactured this year you’ll find hardware built using C synthesis. This session will discuss how C synthesis has been used successfully in mobile devices based on real-world experience. This will include best practices and the key technologies that make HLS a reality in mobile device design as well as hands-on opportunities to try Catapult C. Don’t forget to register: http://www.edatechforum.com/events/

• Tuesday Tech Talk – Enhancing reuse with C++ and HLS

This very practical 30 minute webinar explains how combining C++ language features with High Level Synthesis opens significant new opportunities for design reuse. This is a great opportunity to learn how to leverage the ability to separate functionality and implementation in order to efficiently reuse and retarget technology neutral IP descriptions. The Tuesday Tech Talk page has more details and a link for registration.

• Dan Gardner’s Blog – “Hello World” for Hardware Engineers

My colleague Dan Gardner runs his own blog on C synthesis. Dan talks about all the cool things you do with this technology from a hardware engineering perspective. This blog is great place to learn through examples. His posts have detailed source code, both in C and RTL. In his first post, Dan takes a simple clock dividing counter all the way from C to FPGA. This post is a very valuable reading and a great practical introduction to C synthesis.

These are just a few of the insightful and practical resources on C synthesis. You can find a lot more on the Catapult C web pages. And if you are looking for something specific to get going with C synthesis, don’t hesitate to drop me a comment. I’d love to know what kind of learning material you find most valuable.

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