See ya at the Finish Dad!
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Posted Mar 27, 2010
by Steve Collis
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What is a Go URL?Well the Power Diet almost worked. I managed to finish the fun run this year over a minute and half faster than last year but I told my daughter not to wait for me and she didn’t! “Ok, see ya at the finish Dad”, she says and then goes onto finish nearly a minute faster than me! But what really impressed me this year was my son’s performance. Last year he finished behind us, but this year he went sprinting off at the start and finished a full three minutes ahead of me. I’m pretty sure his increase in height (nearly 20cm) and all the extra Testosterone flowing round his body was a major contribution to this dramatic improvement in performance compared to last year
When your kids start to easily beat you, it does make you feel a bit old, but it also fills you with huge pride to see them growing up to be so strong and fast! In many ways this process of the young outperforming the old and continual improvement is key to the whole success of the human race and especially important in EDA because it is EDA that enables the continual improvements in computing power that underpins all advances in our modern world.
For example: In the past, the creation of the physical implementation (P&R) of a low power chip design involved many tool specific scripts and workarounds to get the physical implementation of the power intent correct. The implementation engineers had to understand the full detail of the power architecture of the design and manually encode this into scripts to create the correct physical implementation. But now, if a UPF description has been developed to describe the power architecture of the chip as part of the front verification flow as discussed in our Power Aware Verification Tuesday Tech Talk, then the same UPF description can be used to drive the physical implementation.
Using the UPF developed in your front end verification flow for your back end implementation flow is the major topic of our next Tuesday Tech Talk
How Physical Implementation realizes Power Intent
I hope you can join us for this and see how the new way is so much better.
About Steve Collis
My first exposure to Electronic Design Tools was at GEC Telecommunications where I manually entered HILO netlists using a DEC vt100 connected to a VAX to simulate a gate array design which eventually became part of a System X telephone exchange. Even though this was tedious work I could see the huge advantages in modelling a design in the computer verses trying to breadboard it in the lab. I was then lucky enough to be able to get involved in the development of early IC physical design system using parameterised language descriptions to build layouts of standard cells.
Later on when I worked at DEC, I was involved in the early wave of RTL design using early language based simulators and synthesis tools and worked on the development of an early VHDL simulator. This early exposure to RTL design brought me to Mentor Graphics where I was lucky enough to be involved the adoption of RTL based design techniques and the significant changes to Gate Array, Asic, SoC and FPGA design techniques that have taken place over the last 20 years or so. More recently I have held various consulting and management positions and today head up a team of product specialist concentrating on high level design and functional verification across Europe.
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