Synthesizing parallel designs from sequential C++ - part 1

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Gravatar Posted Jul 14, 2009
by Thomas Bollaert
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Tags: C++, High-Level Synthesis, Catapult C Synthesis

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It is a fact of life; preconceived ideas tend to live long. But in a rational and scientific domain such as electronic design, it really feels wrong when false statements are repeatedly asserted by engineers themselves.

In EDA, and more specifically in the field of C synthesis, a commonly spread idea is that it is impossible to synthesize parallel hardware designs from sequential C++. The corollary of this thought is that explicit description of concurrency is required in the synthesized source code.

“C++ is inherently sequential. You do A, then B, then C. You can’t get parallel hardware from this”.

At first sight, the strong semantic opposition between “sequential” and “parallel” makes this a tempting proposition to fall for. Luckily this idea doesn’t resist closer examination and proves to be another myth that needs to be busted !  In follow-on posts, I will explain how spatial and temporal parallelism can be extracted from pure C++ to build efficient concurrent hardware.

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But before diving into the technical details, I would just like to point out that for the past 5 years, hundreds of users worldwide have been using Catapult C to synthesize production quality RTL from pure C++. Needless to say that the resulting RTL featured all the needed parallelism.

In a recent ESNUG post (ESNUG 481 Item 7), Slumdog Millionaire explained how he was able to implement a 3GPP-like turbo decoder with Catapult C, starting from pure C++. Turbo decoding requires extensive concurrency to meet high performance requirements. Not only was Slumdog Millionaire able to get the required parallelism from sequential C++, but he was also able to get to verified RTL 60% faster than with manual methods.

So yes, and once and for all, it is possible to synthesize parallel designs from sequential C++.

And if you haven’t fully checked it out yet, be sure to browse our new Catapult C web site at http://www.mentor.com/products/esl/catapult-c. The three online demos might provide additional inspiration on what high-level synthesis from C++ can do for you.

About Thomas Bollaert

imageMy first encounter with HLS, back then behavioural synthesis, dates more than 15 years. Since then my ventures have led me to explore many aspects of the ESL design flow, including HW/SW co-design, architecture exploration and of course, C synthesis. Five years ago, I joined Mentor to develop the Catapult C product line in Europe. Recently, my little family followed me all the way from Paris to Oregon, where I now serve as product marketing manager for Mentor Graphics' high-level synthesis product line. Visit Thomas Bollaert’s Blog

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4 Comments on this Post

Commented on 9:47 PM, Jul 15, 2009
By “This one is right on target” « Thomas Bollaert’s Blog

[...] previous post on synthesizing parallel designs from sequential C++ scratched the surface of an essential question for understanding the potential of HLS. Expect [...]

Commented on 3:21 AM, Jul 16, 2009
By Krishna

/*rant on */ Thanks for the information. As an signal processing guy with minimal background on RTL, , am presented with a multiple of options when searching for ESL - Catapult, Synfora, AccelChip to name a few. I wish there was a third party (like BDTI) who might be able to comment on the various tools and their usability. /* rant off */ Can you please share your thoughts on advantages of Catapult vs . Thanks, Krishna

Commented on 7:14 PM, Jul 16, 2009
By Thomas Bollaert

Hi Krishna, Thanks for your interest in C synthesis and Catapult C. I could split hair discussing nuts, bolts and low-level features. But I'd rather take a higher level view on the differences between HLS tools. All will produce RTL from a higher abstraction description. While there are distinctions in the core synthesis technology, the fundamental differences are to be found in the overall flow, methodology and ecosystem: - Are you looking to synthesize SystemC, plain C or full-blown C++ code? - Are you targeting ASICs, FPGAs or both? - Is low learning curve an important criteria for you? - How valuable tool endorsement and silicon vendor sign-off is for you? - Would you rather invest with a start-up or a major and reliable EDA provider? - What other tools are you using, and which HLS tool best integrates with those? The language question alone is pivotal. Catapult C is the only tool synthesizing pure C++. Pure C++ means that you’ll benefit from all the modern object-oriented design techniques offered by the language. It also means that you won’t suffer from being weighted down by unnecessary details such as explicit timing or parallelism. This response probably not the best place to further elaborate on the other points. But I’ll incidentally point out that according to GarySmithEDA, Catapult has held the #1 position in high-level synthesis for the past 3 years, and by a good margin. And there are many good reasons for that! Thomas

Commented on 6:50 AM, Aug 10, 2009
By Synthesizing parallel designs from sequential C++ - part 3 « Thomas Bollaert’s Blog

[...] C++ could be parallelized to produce high-performance concurrent hardware. In the first two posts (part 1 and part2) I developed the notions of resource bottlenecks and spatial parallelism; in this third [...]

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