Take the High Road to Power-Optimized RTL

The latest edition of Chip Design Magazine features an insightful head-to-head discussion between Atrenta’s Kiran Vittal and Mentor’s Shawn McCloud. The topic: how to best achieve power-optimized RTL. Should low-power optimizations be performed in the RTL? Or is there more potential for power savings when starting from a more abstract design representation? The two industry experts share their viewpoints.

Atrenta’s Kiran Vittal points to the fact that “the earliest that accurate results for power reduction can be obtained is when the technology library has been chosen and simulation testbenches are available. Only with both technology and simulation data can the actual power savings be computed. Before either is available, however, it may be possible to get useful results by simply locating possible power-reduction opportunities and providing a “scorecard” on how much clock gating is done in the various modules of the design.”

Mentor Graphics’s Shawn McCloud advises that “automating the prevailing low-power techniques at a higher abstraction is essential, as it impacts all design activities. It also is the surest way to circumvent the lack of time and expertise found in manual RTL flows. By automating these proven techniques at a high level of abstraction, C synthesis presents vast potential to optimize for power in a manner that cannot be done otherwise.”

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To read the full discussion, open the PDF copy of the full electronic edition and jump to page 9.

This stimulating discussion is nicely complemented by a cover story by Ed Sperling on “Verifying Low-Power Designs” and how coverage models help balance power requirements with budgets, timelines, and effectiveness. This is on page 28.

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