Taking High-Level Synthesis to the Next Level

On June 29, Mentor Graphics’ Catapult C Synthesis team unveiled breakthrough enhancements leading the way to full-chip synthesis. After pioneering C synthesis in 2004 and hierarchical synthesis in 2006, Catapult C now introduces groundbreaking technology around control-logic synthesis and low-power optimizations.

The control-logic synthesis extensions significantly widen the application scope of high-level synthesis, now letting users target full systems comprised of both control and algorithmic blocks in pure C++. Control-logic is neither trivial to model or synthesize. But the real challenge lies in verifying the combination and interaction of control blocks with algorithmic units. Failing to do so in the C++ code postpones the verification effort late in the RTL – certainly not a comfortable position to be in. Mentor Graphics has addressed the problem with a patent-pending verification flow which lets user run the C++ code taking in account the block-level interactions with the exact same accuracy as in the RTL.

In parallel, the new low-power optimizations provide dramatic power reductions by fully automating prevailing low-power design techniques such as multi-level clock gating. Not everyone has the skills or time to analyze each register in a design and write the clock gating code and corresponding control in the RTL. Catapult now automates this task along with other proven power optimization techniques. Thanks to its thorough analysis, Catapult C delivers designs far more optimized than what can be achieved by hand. Using the new multi-level clock-gating optimizations, a customer design can reduce power consumption by up to 90%.

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Catapult C has held the #1 market position in high-level synthesis for the past 3 years as reported by Gary Smith EDA analysis. We believe these new capabilities will make for an even stronger and compelling solution.

We hope you will share our excitement for these major advances in high-level synthesis which for the first time unify control, algorithms and low-power synthesis.  Please let us know what you think.

For more details, come see us in San Francisco, at the 46th DAC, on booth 3567. You can also register for a private suite presentation through Mentor Graphics’ website: http://www.mentor.com/events/design-automation-conference/

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