Tighter flows, lower power, bigger benefits

Whether for creating greener electronic products, complying with environmental regulations or extending a battery-powered device’s operating time; low-power design is becoming a necessity for most new applications. 

Mentor Graphics recently announced significant advances for low-power design through its Catapult C high-level synthesis tool. During the synthesis process, a tool like Catapult C will find an optimal solution that meets the specified function and the required architecture. Doing so gives the C synthesis tool intimate knowledge of the design. This provides great opportunities for optimizations targeting low-power implementations. More specifically, the latest release of Catapult C will automatically perform multi-level clock-gating and facilitate dynamic voltage and frequency scaling.

While those features already provide significant power savings, Mentor Graphics has taken the low-power HLS flow one step further by partnering with Atrenta and Sequence Design, delivering a certified and tightly integrated flow for low-power synthesis, analysis and optimization. Sequence Design hosted a contributed technical article in the July issue of their Cool Circuit newsletter. Atrenta released a press announcement to emphasize our strengthened collaboration. Both publications provide detailed descriptions on the combined flows and bottom-line benefit to the user. 

These flows will jointly be demonstrated at DAC in the Atrenta and Sequence Design suites.

 

• Catapult / Sequence PowerTheater Presentation

         Booth #3455

         Monday July 27^th, 1 - 2pm

         Wednesday July 29^th, 11am - 12pm

         Registrations

 

• Catapult / Atrenta Spyglass Power Presentation

         Booth #1528

         Tuesday July 28^th, 2 - 3pm

         Wednesday July 29^th, 2 - 3pm

         Registrations

 

Truly integrated solutions that fit into existing, standardized flows are mandatory for successful adoption, repeat usage and seamless deployment within organizations. This did not escape STMicroelectronics as they successfully taped-out “more than a dozen ASIC designs with productivity gains from four to ten times faster than with traditional methods” with such a certified and integrated ESL tool flow.

So, if you are seeking solutions to cool down your ASICs, be sure to check our partner sessions at DAC. While there, stop by the Mentor booth  (#3567) and take in a Mentor presentation on our low-power ESL solutions.  And if San Francisco is out of reach for you this year, Mentor’s low-power portal may have just the information you are looking for.

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