TSMC and Mentor collaborate on ESL for Reference Flow 11

When the world’s leading foundry invests time and resources to extend its reference flow with ESL methodologies, this has to be a sign that electronic-system level (ESL) practices have come of age. This announcement is not only the confirmation of the vital importance of ESL for the electronic design community, it is also a strong sign that flows have matured to the point where mainstream designers can reliably adopt these more productive design practices.

TSMC and Mentor Graphics collaborated to propose a complete ESL design, verification and synthesis flow. While the approach acknowledges the different facets of ESL such as architectural exploration, high-level synthesis and virtual prototyping, Mentor and TSMC put special emphasis on model reuse throughout all tasks of the flow and established an OVM-based verification methodology reusable across ESL and RTL. The result of this joint effort is a comprehensive design kit comprising of demo designs, detailed application notes but also synthesis libraries for 65nm and 40nm TSMC low-power processes.

One the key requirement for high-level synthesis is obviously quality-of-results. At 65nm and below, intimate knowledge of the technology details is a requirement to meet timing closure and other goals. Just like rule decks are needed for physical verification, just like RTL synthesis relies on .lib files, HLS tools should be expected to work with libraries to get the crucial timing, area and power information to produce efficient designs. As part of Reference Flow 11, TSMC has developed and characterized synthesis libraries for Catapult C and is making them available to its customers. Taking the collaboration one step further, the TSMC Memory Compiler was also directly integrated in Catapult C allowing designers to easily create memory models as needed through the HLS process.

The verification aspect of the flow was also of central importance in this collaboration. Mentor contributed know-how in SystemVerilog, OVM, SystemC and TLM to deliver on TSMC’s requirement for a verification methodology enforcing reuse across all ESL tasks and RTL. In this flow, the original ESL design and testbench written in C++ or SystemC are considered the reference for later verification activities and are made reusable for RTL testing through an OVM framework. Whether the RTL DUT is synthesized from Catapult or hand-written, the original ESL model of the design is leveraged as a predictor for scoreboarding and the original ESL testbench is reused to generate OVM sequences. Here also the TSMC demo kit provides a detailed step-by-step approach to implement this methodology which extends the reusability of ESL models for RTL verification.

Preparing Recommendations

I sincerely believe that TSMC’s recent decision to add ESL design, verification and synthesis to its reference flow represents a major milestone for the EDA industry. The ESL track in TSMC’s RF11 demonstrates very clearly how by adding more automation and by eliminating duplication of efforts, many errors can be avoided and considerable efforts can be saved.

More Blog Posts

Preparing Recommendations