Blog

8th ESL Symposium: Panelists to discuss trends and report experiences

Posted May 6, 2010, by Thomas Bollaert

Many things jump to mind when I recall last year’s DAC in San Francisco. But I remember really well the scramble to find a seat in the auditorium packed with the 300 other attendees of the ESL Symposium. For sure, this event should not be missed this year either. In Anaheim, and for the 8th year in a row, a panel of industry experts will discuss the driving forces in ESL and share their thoughts and … Read More

Tags: User Testimonial, DAC, Architecture Validation, Vista, High-Level Synthesis, Architecture Design

Does every end have a start?

Posted Apr 12, 2010, by Thomas Bollaert

Does every end have a start? One would think this ought to be case, but on second look things might not be so straightforward. In an electronic design project you can quite easily identify “the end” and several major intermediate milestones, such as shipping the PG tape. But can you as easily define when a project starts? In an academic view of the design flow, there are cleanly designated phases and … Read More

Smoking Peers

Posted Apr 6, 2010, by Thomas Bollaert

 I couldn’t resist a smile when I saw the following headline in a recent newsletter: “Ericsson wins $1.8bn of Chinese deals“. And my smile widened when, a few days later, I read about Ericsson scoring another huge deal in India. The two announcements underscored the significant strides made by the Swedish company in the 4G wireless market. 4G, also known as LTE (Long Term Evolution), refers to the … Read More

Tags: Partner, Catapult C Synthesis

Modern Luddites

Posted Mar 29, 2010, by Thomas Bollaert

Entire bookshelves have been written about the various human attitudes towards the perspective of change. And it is quite intriguing to watch the well know patterns unfurl in a real-life situation. I am just returning from a series of customer visits in Europe, and as it turns out, during this streak, I got to experience nearly the exact same conversation in two different meetings.  “High-level synthesis … Read More

Tags: High-Level Synthesis

See ya at the Finish Dad!

Posted Mar 27, 2010, by Steve Collis

Well the Power Diet  almost worked.  I managed to finish the fun run this year over a minute and half faster than last year but I told my daughter not to wait for me and she didn’t!  “Ok, see ya at the finish Dad”, she says and then goes onto finish nearly a minute faster than me! But what really impressed me this year was my son’s performance.  Last year he finished behind us, but this year he went … Read More

DesignCon 2010 Paper Award Winners

Posted Mar 11, 2010, by Thomas Bollaert

DesignCon is a major event for EEs working on leading edge hardware design and semiconductor activities. The event takes place annually in the Silicon Valley and it’s never a waste of time to attend it. After each conference, the organizing International Engineering Consortium (IEC) designates DesignCon Paper Award Winners. And it’s quite insightful to see which papers and which kind of topics receive … Read More

DVCon: All About Higher-Level

Posted Mar 2, 2010, by Thomas Bollaert

Well maybe it’s because I’m biased. Maybe because that’s how think. But at last week’s DVCon it really felt that it was all about high-level languages and higher-levels of abstraction to address the “D” and “V” challenges. The titles in the tutorial and session programs were pretty explicit. SystemC and C++ were covered in most presentations, when it wasn’t SystemVerilog or better; a combination of … Read More

Tags: Verification, Partner, Gary Smith

The “S” in ASIC

Posted Feb 25, 2010, by Thomas Bollaert

What does it take to build an ASIC? What role does ESL play in this process? And what will things look like 20 years from now? In a recent post, Synopsys’ Frank Schirrmeister predicts that IP and re-use will play a “crucial role” and suggests that ASIC design may very well be simplified to a mere assembly of standardized components. In an analogy with urban planning, the Oakland harbor is compared to … Read More

Application-specific approaches to ESL

Posted Feb 16, 2010, by Thomas Bollaert

Different design types generate different challenges and trigger different modeling and specification needs. SystemC is C++ class library which, most notably, adds support for timing and concurrency, two features not available from ANSI C++. When it comes to describing actual hardware, these are two critical aspects which must be taken in account through modeling and simulation. But at the specification … Read More

Tags: ANSI C++, SystemC

Big in Japan

Posted Feb 16, 2010, by Thomas Bollaert

The recent launch of Catapult’s new SystemC support at EDSFair in Yokohama was also an opportunity to confirm a long lasting EDA trend: SystemC is big in Japan. Since SystemC’s debuts a decade ago, Japanese companies have always been at the forefront of the user community and, consequently, constituting an important market for ESL products. But acknowledging the fact doesn’t do us much good if the … Read More

Tags: High-Level Synthesis, SystemC, Catapult C Synthesis